Bitline (BL) charge-recycling-based static random access memory (SRAM) write assist circuits (BCR-WA) are proposed to reduce the minimum operating voltage (V MIN ) of SRAM. In the proposed schemes, the charges stored on the unselected BL are utilized to raise the cell ground voltage (VSS) of the selected bit cell, and the increased cell VSS (CVSS) enhances the write ability. According to the metal routing direction of CVSS in the layout, two types of BCR-WA are proposed, BCR-WA for vertical CVSS routing (BCR-WA V ) and horizontal CVSS routing (BCR-WA H ). To evaluate the proposed circuits, HSPICE simulations are performed and the test chip is implemented using a 14-nm FinFET technology. Thanks to the charge-recycling operation, BCR-WA V and BCR-WA H can save energy by 11%-44% and 30%-66%, respectively, compared to the previous write assist circuits, with a comparable or less area overhead and an insignificant degradation in read performance (<1%) and stability (∼25-mV degradation in maximum word-lin voltage). In addition, according to simulation results, BCR-WA V and BCR-WA H can lower V MIN by 150 mV. In particular, silicon measurement result for BCR-WA H proves an 125-mV improvement in V MIN .
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering