Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM

Hanwool Jeong, Juhyun Park, Tae Woo Oh, Woojin Rim, Taejoong Song, Gyuhong Kim, Hyo Sig Won, Seong Ook Jung

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline precharge level in the proposed scheme, the read stability is improved, as compared with that of the conventional scheme. Thus, a higher wordline voltage can be used to further improve the speed. Consequently, the delay and energy in the bitline are reduced by 1.85-5.88 times and 35%-70%, respectively, according to the supply voltage and number of cells per bitline, with a negligible area overhead of 0.9%.

Original languageEnglish
Article number7442809
Pages (from-to)1059-1063
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume63
Issue number11
DOIs
Publication statusPublished - 2016 Nov 1

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Static random access storage
Electric potential
Transistors
Switches

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Jeong, Hanwool ; Park, Juhyun ; Oh, Tae Woo ; Rim, Woojin ; Song, Taejoong ; Kim, Gyuhong ; Won, Hyo Sig ; Jung, Seong Ook. / Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. In: IEEE Transactions on Circuits and Systems II: Express Briefs. 2016 ; Vol. 63, No. 11. pp. 1059-1063.
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abstract = "A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline precharge level in the proposed scheme, the read stability is improved, as compared with that of the conventional scheme. Thus, a higher wordline voltage can be used to further improve the speed. Consequently, the delay and energy in the bitline are reduced by 1.85-5.88 times and 35{\%}-70{\%}, respectively, according to the supply voltage and number of cells per bitline, with a negligible area overhead of 0.9{\%}.",
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Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. / Jeong, Hanwool; Park, Juhyun; Oh, Tae Woo; Rim, Woojin; Song, Taejoong; Kim, Gyuhong; Won, Hyo Sig; Jung, Seong Ook.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 11, 7442809, 01.11.2016, p. 1059-1063.

Research output: Contribution to journalArticle

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