As advances in technology make integrating more transistors on a single integrated circuit (IC) feasible, test data volume becomes one of major factors of testing system-on-chips (SoCs). The large volume of test data leads to increasing test application time and needs more expensive Automatic test equipment (ATE) with high memory. In this paper, we present broadcast scan compression based on deterministic pattern generation algorithm to reduce the volume of test data. The proposed method further improves compression ratio of the volume of test data by exploiting advances of both broadcast scan compression and pattern generation using linear feedback shift register (LFSR). The volume of test data can be reduced by feeding multiple scan chains from a few LFSRs and by compressing the data using LFSRs. ISCAS'89 benchmark circuits verify the proposed method and the experimental results show that the compression ratio is up to 10× which means test application time also is reduced extremely.
|Title of host publication||Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017|
|Publisher||IEEE Computer Society|
|Number of pages||5|
|Publication status||Published - 2017 May 2|
|Event||18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States|
Duration: 2017 Mar 14 → 2017 Mar 15
|Name||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Other||18th International Symposium on Quality Electronic Design, ISQED 2017|
|Period||17/3/14 → 17/3/15|
Bibliographical notePublisher Copyright:
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality