We propose an approach called buffered compares, a less-invasive processing-in-memory solution that can be used with existing processor memory interfaces such as DDR3/4 with minimal changes. The approach is based on the observation that multi-bank architecture, a key feature of modern main memory DRAM devices, can be used to provide huge internal bandwidth without any major modification. We place a small buffer and a simple ALU per bank, define a set of new DRAM commands to fill the buffer and feed data to the ALU, and return the result for a set of commands (not for each command) to the host memory controller. By exploiting the under-utilized internal bandwidth using 'compare-n-op' operations, which are frequently used in many applications, we not only reduce the amount of energy-inefficient processor-memory communication, but also accelerate the computation of big data processing applications by utilizing parallelism of the buffered compare units in DRAM banks. Experimental results show that our solution significantly improves the performance and efficiency of the system on the tested workloads.
|Title of host publication||Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|Publication status||Published - 2016 Apr 25|
|Event||19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany|
Duration: 2016 Mar 14 → 2016 Mar 18
|Name||Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016|
|Conference||19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016|
|Period||16/3/14 → 16/3/18|
Bibliographical noteFunding Information:
This work was supported by an IBM Open Collaborative Faculty Award, Samsung Electronics (SNU-490-20150004) and the National Research Foundation of Korea grant funded by the Korea government (NRF-2014R1A2A1A11052936).
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Safety, Risk, Reliability and Quality