Built-in self test for content addressable memories

Yong Seok Kang, Jong Cheol Lee, Sungho Kang

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

A new parallel test algorithm and a Built-in Self Test (BIST) architecture for an efficient testing of various types of functional faults in Content Addressable Memories (CAMs) are developed. In test mode, the read operation is replaced by one parallel content addressable search operation and the writing operation is performed parallely with small peripheral circuit modifications. The results show that an efficient and practical testing with very low complexity and area overhead can be achieved.

Original languageEnglish
Pages48-53
Number of pages6
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 International Conference on Computer Design - Austin, TX, USA
Duration: 1997 Oct 121997 Oct 15

Other

OtherProceedings of the 1997 International Conference on Computer Design
CityAustin, TX, USA
Period97/10/1297/10/15

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Kang, Y. S., Lee, J. C., & Kang, S. (1997). Built-in self test for content addressable memories. 48-53. Paper presented at Proceedings of the 1997 International Conference on Computer Design, Austin, TX, USA, .