Built-in self-test implementation for an analog-to-digital converter

Kwisung Yoo, Minho Kwon, Geumhwan Bahng, Sangyun Hwang, Hoon Lee, Jungyoon Lee, Daesik Seo, Jaeseok Kim, Sungho Kang, Gunhee Han

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


As integrated circuit fabrication techniques advance, a complex system can be integrated on a single chip: namely, a system-on-a-chip (SOC). A SOC consists of many intellectual property (IP) building blocks, including analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) which should provide certain built-in self-test (BIST) scheme to minimize the testing cost. Due to the analog nature of ADCs and DACs, digital BIST schemes are not applicable. This paper proposes a simple ADC BIST scheme based on a ramp test. The proposed BIST scheme is verified by simulation with a 6-bit pipelined ADC. Simulation results show that the proposed ADC BIST scheme can detect not only catastrophic faults but also some parametric faults. The total gate count of the proposed BIST circuit is about 150.

Original languageEnglish
Pages (from-to)963-966
Number of pages4
JournalJournal of the Korean Physical Society
Issue number6
Publication statusPublished - 2002 Dec

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy(all)


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