As integrated circuit fabrication techniques advance, a complex system can be integrated on a single chip: namely, a system-on-a-chip (SOC). A SOC consists of many intellectual property (IP) building blocks, including analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) which should provide certain built-in self-test (BIST) scheme to minimize the testing cost. Due to the analog nature of ADCs and DACs, digital BIST schemes are not applicable. This paper proposes a simple ADC BIST scheme based on a ramp test. The proposed BIST scheme is verified by simulation with a 6-bit pipelined ADC. Simulation results show that the proposed ADC BIST scheme can detect not only catastrophic faults but also some parametric faults. The total gate count of the proposed BIST circuit is about 150.
|Number of pages||4|
|Journal||Journal of the Korean Physical Society|
|Publication status||Published - 2002 Dec 1|
All Science Journal Classification (ASJC) codes
- Physics and Astronomy(all)