Abstract
Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multilevel cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes consist of three procedures, estimation of cell-to-cell interference, compensation for cell-to-cell interference, and generation of log-likelihood ratio (LLR). First, reduced symbol pattern of interfering cells is used to estimate cell-to-cell interference by modifying the levels of the threshold voltage shift from multi page programming to two levels. Second, based on this estimation, cell-to-cell interference is compensated by modifying the read voltage considering the estimated cell-to-cell interference in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check (LDPC) codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, cell-to-cell interference can be relaxed with a simple structure and a high reliability. The bit error rate (BER) performances of the proposed schemes are compared with the conventional schemes on 8-level MLC NAND flash memory. Simulation results show that the proposed schemes show the improved BER performances by more than an order of magnitude compared with the conventional LDPC scheme.
| Original language | English |
|---|---|
| Article number | 6522273 |
| Pages (from-to) | 2569-2573 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Magnetics |
| Volume | 49 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 2013 Jun 14 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. / Kim, Taehyung; Kong, Gyuyeol; Weiya, Xi; Choi, Sooyong.
In: IEEE Transactions on Magnetics, Vol. 49, No. 6, 6522273, 14.06.2013, p. 2569-2573.Research output: Contribution to journal › Article
TY - JOUR
T1 - Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory
AU - Kim, Taehyung
AU - Kong, Gyuyeol
AU - Weiya, Xi
AU - Choi, Sooyong
PY - 2013/6/14
Y1 - 2013/6/14
N2 - Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multilevel cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes consist of three procedures, estimation of cell-to-cell interference, compensation for cell-to-cell interference, and generation of log-likelihood ratio (LLR). First, reduced symbol pattern of interfering cells is used to estimate cell-to-cell interference by modifying the levels of the threshold voltage shift from multi page programming to two levels. Second, based on this estimation, cell-to-cell interference is compensated by modifying the read voltage considering the estimated cell-to-cell interference in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check (LDPC) codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, cell-to-cell interference can be relaxed with a simple structure and a high reliability. The bit error rate (BER) performances of the proposed schemes are compared with the conventional schemes on 8-level MLC NAND flash memory. Simulation results show that the proposed schemes show the improved BER performances by more than an order of magnitude compared with the conventional LDPC scheme.
AB - Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multilevel cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes consist of three procedures, estimation of cell-to-cell interference, compensation for cell-to-cell interference, and generation of log-likelihood ratio (LLR). First, reduced symbol pattern of interfering cells is used to estimate cell-to-cell interference by modifying the levels of the threshold voltage shift from multi page programming to two levels. Second, based on this estimation, cell-to-cell interference is compensated by modifying the read voltage considering the estimated cell-to-cell interference in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check (LDPC) codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, cell-to-cell interference can be relaxed with a simple structure and a high reliability. The bit error rate (BER) performances of the proposed schemes are compared with the conventional schemes on 8-level MLC NAND flash memory. Simulation results show that the proposed schemes show the improved BER performances by more than an order of magnitude compared with the conventional LDPC scheme.
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U2 - 10.1109/TMAG.2013.2251417
DO - 10.1109/TMAG.2013.2251417
M3 - Article
AN - SCOPUS:84878780950
VL - 49
SP - 2569
EP - 2573
JO - IEEE Transactions on Magnetics
JF - IEEE Transactions on Magnetics
SN - 0018-9464
IS - 6
M1 - 6522273
ER -