Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory

G. Kong, T. Kim, W. Xi, Sooyong Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multi-level cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes contain three signal-processing techniques, estimating cell-to-cell interference, compensating cell-to-cell interference, and generating log-likelihood ratio (LLR). Firstly, reduced symbol pattern of interfering cells is used to easily estimate cell-to-cell interference by setting threshold voltage shift to be only two values in the programming state. Based on this estimation, cell-to-cell interference is compensated by modifying the read voltage in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, the interference can be relaxed with a simpler structure and a higher reliability compared to the conventional methods for MLC NAND flash memory.

Original languageEnglish
Title of host publication2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference
Subtitle of host publicationA Strong Tradition. An Exciting New Look!
Publication statusPublished - 2012 Dec 1
Event2012 Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!, APMRC 2012 - Singapore, Singapore
Duration: 2012 Oct 312012 Nov 2

Publication series

Name2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!

Other

Other2012 Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!, APMRC 2012
CountrySingapore
CitySingapore
Period12/10/3112/11/2

Fingerprint

Flash memory
Electric potential
Threshold voltage
Signal processing
Compensation and Redress

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials

Cite this

Kong, G., Kim, T., Xi, W., & Choi, S. (2012). Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. In 2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look! [6407527] (2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!).
Kong, G. ; Kim, T. ; Xi, W. ; Choi, Sooyong. / Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. 2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!. 2012. (2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!).
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abstract = "Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multi-level cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes contain three signal-processing techniques, estimating cell-to-cell interference, compensating cell-to-cell interference, and generating log-likelihood ratio (LLR). Firstly, reduced symbol pattern of interfering cells is used to easily estimate cell-to-cell interference by setting threshold voltage shift to be only two values in the programming state. Based on this estimation, cell-to-cell interference is compensated by modifying the read voltage in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, the interference can be relaxed with a simpler structure and a higher reliability compared to the conventional methods for MLC NAND flash memory.",
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Kong, G, Kim, T, Xi, W & Choi, S 2012, Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. in 2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!., 6407527, 2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!, 2012 Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!, APMRC 2012, Singapore, Singapore, 12/10/31.

Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. / Kong, G.; Kim, T.; Xi, W.; Choi, Sooyong.

2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!. 2012. 6407527 (2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multi-level cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes contain three signal-processing techniques, estimating cell-to-cell interference, compensating cell-to-cell interference, and generating log-likelihood ratio (LLR). Firstly, reduced symbol pattern of interfering cells is used to easily estimate cell-to-cell interference by setting threshold voltage shift to be only two values in the programming state. Based on this estimation, cell-to-cell interference is compensated by modifying the read voltage in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, the interference can be relaxed with a simpler structure and a higher reliability compared to the conventional methods for MLC NAND flash memory.

AB - Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multi-level cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes contain three signal-processing techniques, estimating cell-to-cell interference, compensating cell-to-cell interference, and generating log-likelihood ratio (LLR). Firstly, reduced symbol pattern of interfering cells is used to easily estimate cell-to-cell interference by setting threshold voltage shift to be only two values in the programming state. Based on this estimation, cell-to-cell interference is compensated by modifying the read voltage in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, the interference can be relaxed with a simpler structure and a higher reliability compared to the conventional methods for MLC NAND flash memory.

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M3 - Conference contribution

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Kong G, Kim T, Xi W, Choi S. Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. In 2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!. 2012. 6407527. (2012 Digest APMRC - Asia-Pacific Magnetic Recording Conference: A Strong Tradition. An Exciting New Look!).