Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation

Jaewon Jang, Minho Cheong, Jin Ho Ahn, Sung Kyu Lim, Sungho Kang

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.

Original languageEnglish
Article number7747508
Pages (from-to)1178-1182
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number3
DOIs
Publication statusPublished - 2017 Mar

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2015R1A2A1A13001751).

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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