A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.
|Number of pages||5|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2017 Mar|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2015R1A2A1A13001751).
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering