Abstract
Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.
| Original language | English |
|---|---|
| Pages (from-to) | 3424-3427 |
| Number of pages | 4 |
| Journal | Microelectronic Engineering |
| Volume | 88 |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - 2011 Dec 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering
Cite this
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Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor. / Choi, Won Ho; Oh, Jungwoo; Yoo, Ook Sang; Han, In Shik; Na, Min Ki; Kwon, Hyuk Min; Park, Byung Suk; Majhi, P.; Tseng, H. H.; Jammy, R.; Lee, Hi Deok.
In: Microelectronic Engineering, Vol. 88, No. 12, 01.12.2011, p. 3424-3427.Research output: Contribution to journal › Article
TY - JOUR
T1 - Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor
AU - Choi, Won Ho
AU - Oh, Jungwoo
AU - Yoo, Ook Sang
AU - Han, In Shik
AU - Na, Min Ki
AU - Kwon, Hyuk Min
AU - Park, Byung Suk
AU - Majhi, P.
AU - Tseng, H. H.
AU - Jammy, R.
AU - Lee, Hi Deok
PY - 2011/12/1
Y1 - 2011/12/1
N2 - Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.
AB - Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.
UR - http://www.scopus.com/inward/record.url?scp=81855226449&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=81855226449&partnerID=8YFLogxK
U2 - 10.1016/j.mee.2009.11.019
DO - 10.1016/j.mee.2009.11.019
M3 - Article
AN - SCOPUS:81855226449
VL - 88
SP - 3424
EP - 3427
JO - Microelectronic Engineering
JF - Microelectronic Engineering
SN - 0167-9317
IS - 12
ER -