Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Won Ho Choi; Jungwoo Oh; Ook Sang Yoo; In Shik Han; Min Ki Na; Hyuk Min Kwon; Byung Suk Park; P. Majhi; H. H. Tseng; R. Jammy; Hi Deok Lee

doi:10.1016/j.mee.2009.11.019

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Won Ho Choi, Jungwoo Oh, Ook Sang Yoo, In Shik Han, Min Ki Na, Hyuk Min Kwon, Byung Suk Park, P. Majhi, H. H. Tseng, R. Jammy, Hi Deok Lee

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

Original language	English
Pages (from-to)	3424-3427
Number of pages	4
Journal	Microelectronic Engineering
Volume	88
Issue number	12
DOIs	https://doi.org/10.1016/j.mee.2009.11.019
Publication status	Published - 2011 Dec

Bibliographical note

Funding Information:
This work was supported in part by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2007-612-D00107). This work is also supported in part by the Ministry of Knowledge Economy (MKE) and Korea Industrial Technology Foundation (KOTEF) through the Human Resource Training Project for Strategic Technology.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/j.mee.2009.11.019

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title = "Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor",

abstract = "Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.",

author = "Choi, {Won Ho} and Jungwoo Oh and Yoo, {Ook Sang} and Han, {In Shik} and Na, {Min Ki} and Kwon, {Hyuk Min} and Park, {Byung Suk} and P. Majhi and Tseng, {H. H.} and R. Jammy and Lee, {Hi Deok}",

note = "Funding Information: This work was supported in part by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2007-612-D00107). This work is also supported in part by the Ministry of Knowledge Economy (MKE) and Korea Industrial Technology Foundation (KOTEF) through the Human Resource Training Project for Strategic Technology.",

year = "2011",

month = dec,

doi = "10.1016/j.mee.2009.11.019",

language = "English",

volume = "88",

pages = "3424--3427",

journal = "Microelectronic Engineering",

issn = "0167-9317",

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TY - JOUR

T1 - Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

AU - Choi, Won Ho

AU - Oh, Jungwoo

AU - Yoo, Ook Sang

AU - Han, In Shik

AU - Na, Min Ki

AU - Kwon, Hyuk Min

AU - Park, Byung Suk

AU - Majhi, P.

AU - Tseng, H. H.

AU - Jammy, R.

AU - Lee, Hi Deok

N1 - Funding Information: This work was supported in part by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2007-612-D00107). This work is also supported in part by the Ministry of Knowledge Economy (MKE) and Korea Industrial Technology Foundation (KOTEF) through the Human Resource Training Project for Strategic Technology.

PY - 2011/12

Y1 - 2011/12

N2 - Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

AB - Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

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DO - 10.1016/j.mee.2009.11.019

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VL - 88

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EP - 3427

JO - Microelectronic Engineering

JF - Microelectronic Engineering

SN - 0167-9317

IS - 12

ER -

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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