Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Won Ho Choi, Jungwoo Oh, Ook Sang Yoo, In Shik Han, Min Ki Na, Hyuk Min Kwon, Byung Suk Park, P. Majhi, H. H. Tseng, R. Jammy, Hi Deok Lee

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

Original languageEnglish
Pages (from-to)3424-3427
Number of pages4
JournalMicroelectronic Engineering
Issue number12
Publication statusPublished - 2011 Dec

Bibliographical note

Funding Information:
This work was supported in part by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2007-612-D00107). This work is also supported in part by the Ministry of Knowledge Economy (MKE) and Korea Industrial Technology Foundation (KOTEF) through the Human Resource Training Project for Strategic Technology.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


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