Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Won Ho Choi, Jungwoo Oh, Ook Sang Yoo, In Shik Han, Min Ki Na, Hyuk Min Kwon, Byung Suk Park, P. Majhi, H. H. Tseng, R. Jammy, Hi Deok Lee

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

Original languageEnglish
Pages (from-to)3424-3427
Number of pages4
JournalMicroelectronic Engineering
Volume88
Issue number12
DOIs
Publication statusPublished - 2011 Dec 1

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

Choi, W. H., Oh, J., Yoo, O. S., Han, I. S., Na, M. K., Kwon, H. M., Park, B. S., Majhi, P., Tseng, H. H., Jammy, R., & Lee, H. D. (2011). Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor. Microelectronic Engineering, 88(12), 3424-3427. https://doi.org/10.1016/j.mee.2009.11.019