Check-bit-reduced codewords using non-2n data bits for ECC-based self-refresh enhancement techniques in DRAMs

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Abstract

Error correction code (ECC) techniques have often been used to reduce the self-refresh power of dynamic random access memories (DRAMs). However, the overhead associated with the large number of check bits has prevented ECC methods from being incorporated into commercial applications. In a novel approach employed in this reported work, the number of data bits in the proposed codeword is set to have a length that is not a power of two (non-2 n). Such a condition results in a substantial decrease in the number of required check bits. Compared to the use of 2n data bits in 1Gb DRAMs, implementations that utilise the proposed codeword can achieve ECC-enhanced self-refresh schemes with 3.4 and 4.7 reductions in check bit and register overheads, respectively.

Original languageEnglish
Pages (from-to)1488-1490
Number of pages3
JournalElectronics Letters
Volume46
Issue number22
DOIs
Publication statusPublished - 2010 Oct 28

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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