TY - GEN
T1 - Clock and data recovery circuit using digital phase aligner and phase interpolator
AU - Lee, Seung Woo
AU - Seong, Chang Kyung
AU - Choi, Woo Young
AU - Lee, Bhum Cheol
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2006
Y1 - 2006
N2 - Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 7-1 FRBS with no error.
AB - Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 7-1 FRBS with no error.
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U2 - 10.1109/MWSCAS.2006.382156
DO - 10.1109/MWSCAS.2006.382156
M3 - Conference contribution
AN - SCOPUS:34748878775
SN - 1424401739
SN - 9781424401734
T3 - Midwest Symposium on Circuits and Systems
SP - 690
EP - 693
BT - Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
T2 - 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
Y2 - 6 August 2006 through 9 August 2007
ER -