Clock and data recovery circuit using digital phase aligner and phase interpolator

Seung Woo Lee, Chang Kyung Seong, Woo Young Choi, Bhum Cheol Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 7-1 FRBS with no error.

Original languageEnglish
Title of host publicationProceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
Pages690-693
Number of pages4
DOIs
Publication statusPublished - 2006
Event2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06 - San Juan, Puerto Rico
Duration: 2006 Aug 62007 Aug 9

Publication series

NameMidwest Symposium on Circuits and Systems
Volume1
ISSN (Print)1548-3746

Other

Other2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
CountryPuerto Rico
CitySan Juan
Period06/8/607/8/9

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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