Clock and data recovery circuit using digital phase aligner and phase interpolator

Seung Woo Lee; Chang Kyung Seong; Woo Young Choi; Bhum Cheol Lee

doi:10.1109/MWSCAS.2006.382156

Clock and data recovery circuit using digital phase aligner and phase interpolator

Seung Woo Lee, Chang Kyung Seong, Woo Young Choi, Bhum Cheol Lee

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um² with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 ⁷-1 FRBS with no error.

Original language	English
Title of host publication	Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
Pages	690-693
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2006.382156
Publication status	Published - 2006
Event	2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06 - San Juan, Puerto Rico Duration: 2006 Aug 6 → 2007 Aug 9

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	1
ISSN (Print)	1548-3746

Other

Other	2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
Country	Puerto Rico
City	San Juan
Period	06/8/6 → 07/8/9

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2006.382156

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title = "Clock and data recovery circuit using digital phase aligner and phase interpolator",

abstract = "Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 7-1 FRBS with no error.",

author = "Lee, {Seung Woo} and Seong, {Chang Kyung} and Choi, {Woo Young} and Lee, {Bhum Cheol}",

year = "2006",

doi = "10.1109/MWSCAS.2006.382156",

language = "English",

isbn = "1424401739",

series = "Midwest Symposium on Circuits and Systems",

pages = "690--693",

booktitle = "Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06",

note = "2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06 ; Conference date: 06-08-2006 Through 09-08-2007",

}

Lee, SW, Seong, CK, Choi, WY & Lee, BC 2006, Clock and data recovery circuit using digital phase aligner and phase interpolator. in Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06., 4267233, Midwest Symposium on Circuits and Systems, vol. 1, pp. 690-693, 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06, San Juan, Puerto Rico, 06/8/6. https://doi.org/10.1109/MWSCAS.2006.382156

Clock and data recovery circuit using digital phase aligner and phase interpolator. / Lee, Seung Woo; Seong, Chang Kyung; Choi, Woo Young; Lee, Bhum Cheol.

Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06. 2006. p. 690-693 4267233 (Midwest Symposium on Circuits and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Clock and data recovery circuit using digital phase aligner and phase interpolator

AU - Lee, Seung Woo

AU - Seong, Chang Kyung

AU - Choi, Woo Young

AU - Lee, Bhum Cheol

PY - 2006

Y1 - 2006

N2 - Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 7-1 FRBS with no error.

AB - Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 7-1 FRBS with no error.

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T3 - Midwest Symposium on Circuits and Systems

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BT - Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06

T2 - 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06

Y2 - 6 August 2006 through 9 August 2007

ER -

Clock and data recovery circuit using digital phase aligner and phase interpolator

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