CMOS four quadrant current/transconductance multiplier

Alejandro Diaz-Sanchez, Jaime Ramirez-Angulo, Edgar Sanchez-Sinencio, Gunhee Han

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based in the square-law characteristic of MOS transistors in saturation region. SPICE simulations with 2 μm CMOS parameters are shown that verify the operation of the circuit.

Original languageEnglish
Pages237-240
Number of pages4
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA
Duration: 1997 Aug 31997 Aug 6

Other

OtherProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
CitySacramento, CA, USA
Period97/8/397/8/6

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Diaz-Sanchez, A., Ramirez-Angulo, J., Sanchez-Sinencio, E., & Han, G. (1997). CMOS four quadrant current/transconductance multiplier. 237-240. Paper presented at Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .