Abstract
This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based in the square-law characteristic of MOS transistors in saturation region. SPICE simulations with 2 μm CMOS parameters are shown that verify the operation of the circuit.
| Original language | English |
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| Pages | 237-240 |
| Number of pages | 4 |
| Publication status | Published - 1997 Dec 1 |
| Event | Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA Duration: 1997 Aug 3 → 1997 Aug 6 |
Other
| Other | Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) |
|---|---|
| City | Sacramento, CA, USA |
| Period | 97/8/3 → 97/8/6 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Diaz-Sanchez, A., Ramirez-Angulo, J., Sanchez-Sinencio, E., & Han, G. (1997). CMOS four quadrant current/transconductance multiplier. 237-240. Paper presented at Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .