CMOS scaling for the next decade

Trends, challenges and opportunities

Prashant Majhi, Jungwoo Oh, Se Hoon Lee, Rusty Harris, Hsing Huang Tseng, Raj Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The advent of high-k/metal gates into production for CMOS gate stacks has marked the onset of MOSFET scaling that has clearly become reliant on new materials and / or new device architecture. Additionally, new approaches to form ultra-shallow junctions with high active-dopant concentrations and low schottky barrier height silicides with novel materials to reduce contact resistance have been reported by many groups and will continue to facilitate MOSFET scaling with increasing performance. It is becoming clear that Si (as the channel) may not be able to provide for the high performance combined with low power technologies that would be needed in future. Over several years, there has been a lot of research on high mobility channels: group IV for pMOSFETs and III-V for NMOSFETs. However, there appears to be little consensus on a) the choice of high mobility channels for P and N channel MOSFETs, b) its potential compared to short channel strained-Si, and 3) potential technology node for insertion. In this work, trends, challenges and opportunities related to several of the aforementioned modules (gate stack, junctions, contacts, and high mobility Ge based channels) will be briefly presented and discussed.

Original languageEnglish
Title of host publicationECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages253-262
Number of pages10
Volume13
Edition1
DOIs
Publication statusPublished - 2008 Nov 13
EventAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4 - Phoenix, AZ, United States
Duration: 2008 May 182008 May 22

Other

OtherAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4
CountryUnited States
CityPhoenix, AZ
Period08/5/1808/5/22

Fingerprint

Silicides
Contact resistance
Doping (additives)
Metals

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Majhi, P., Oh, J., Lee, S. H., Harris, R., Tseng, H. H., & Jammy, R. (2008). CMOS scaling for the next decade: Trends, challenges and opportunities. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment (1 ed., Vol. 13, pp. 253-262) https://doi.org/10.1149/1.2911506
Majhi, Prashant ; Oh, Jungwoo ; Lee, Se Hoon ; Harris, Rusty ; Tseng, Hsing Huang ; Jammy, Raj. / CMOS scaling for the next decade : Trends, challenges and opportunities. ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. Vol. 13 1. ed. 2008. pp. 253-262
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Majhi, P, Oh, J, Lee, SH, Harris, R, Tseng, HH & Jammy, R 2008, CMOS scaling for the next decade: Trends, challenges and opportunities. in ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1 edn, vol. 13, pp. 253-262, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4, Phoenix, AZ, United States, 08/5/18. https://doi.org/10.1149/1.2911506

CMOS scaling for the next decade : Trends, challenges and opportunities. / Majhi, Prashant; Oh, Jungwoo; Lee, Se Hoon; Harris, Rusty; Tseng, Hsing Huang; Jammy, Raj.

ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. Vol. 13 1. ed. 2008. p. 253-262.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Majhi P, Oh J, Lee SH, Harris R, Tseng HH, Jammy R. CMOS scaling for the next decade: Trends, challenges and opportunities. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1 ed. Vol. 13. 2008. p. 253-262 https://doi.org/10.1149/1.2911506