CMOS scaling with III-V channels for improved performance and low power

R. J.W. Hill, Jungwoo Oh, C. Park, J. Barnett, J. Price, J. Huang, N. Goel, W. Y. Loh, P. Kirsch, P. Majhi, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the module targets and challenges for III-V materials to be successfully integrated for high performance/low power logic at or beyond the 11 nm technology node. A VLSI compatible, self-aligned, III-V on 200mm Si MOSFET process flow is presented using an industry standard toolset. Statistically significant data shows that III-V devices can be processed on a Si line with controlled contamination, good uniformity and yield. The Lg = 500 nm device has a drive current of 471 μA/μm (Vgs = Vds = 1V) and intrinsic transconductance of 1005 μS/um.

Original languageEnglish
Title of host publicationDielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3
Pages335-344
Number of pages10
Edition3
DOIs
Publication statusPublished - 2011 Aug 1
EventGraphene Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications - 3 - 219th ECS Meeting - Montreal, QC, Canada
Duration: 2011 May 22011 May 4

Publication series

NameECS Transactions
Number3
Volume35
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherGraphene Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications - 3 - 219th ECS Meeting
CountryCanada
CityMontreal, QC
Period11/5/211/5/4

Fingerprint

Transconductance
Transport properties
Contamination
Industry

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Hill, R. J. W., Oh, J., Park, C., Barnett, J., Price, J., Huang, J., ... Jammy, R. (2011). CMOS scaling with III-V channels for improved performance and low power. In Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3 (3 ed., pp. 335-344). (ECS Transactions; Vol. 35, No. 3). https://doi.org/10.1149/1.3569926
Hill, R. J.W. ; Oh, Jungwoo ; Park, C. ; Barnett, J. ; Price, J. ; Huang, J. ; Goel, N. ; Loh, W. Y. ; Kirsch, P. ; Majhi, P. ; Jammy, R. / CMOS scaling with III-V channels for improved performance and low power. Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3. 3. ed. 2011. pp. 335-344 (ECS Transactions; 3).
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Hill, RJW, Oh, J, Park, C, Barnett, J, Price, J, Huang, J, Goel, N, Loh, WY, Kirsch, P, Majhi, P & Jammy, R 2011, CMOS scaling with III-V channels for improved performance and low power. in Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3. 3 edn, ECS Transactions, no. 3, vol. 35, pp. 335-344, Graphene Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications - 3 - 219th ECS Meeting, Montreal, QC, Canada, 11/5/2. https://doi.org/10.1149/1.3569926

CMOS scaling with III-V channels for improved performance and low power. / Hill, R. J.W.; Oh, Jungwoo; Park, C.; Barnett, J.; Price, J.; Huang, J.; Goel, N.; Loh, W. Y.; Kirsch, P.; Majhi, P.; Jammy, R.

Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3. 3. ed. 2011. p. 335-344 (ECS Transactions; Vol. 35, No. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Hill RJW, Oh J, Park C, Barnett J, Price J, Huang J et al. CMOS scaling with III-V channels for improved performance and low power. In Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3. 3 ed. 2011. p. 335-344. (ECS Transactions; 3). https://doi.org/10.1149/1.3569926