Real-time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been available for some time, the CMOS multiplier implementation is still a challenging subject especially for low-voltage and low-power circuit design. Despite the large number of papers proposing new MOS multiplier structures, they can be roughly grouped into a few categories. This tutorial provides a complete survey of CMOS multipliers, presents a unified generation of multiplier architectures, and proposes the most recommended MOS multiplier structure. This tutorial could serve as a starting reference point (and metric) for comparison of new CMOS multiplier circuit configurations. An illustrative CMOS chip prototype verifying theoretical results is presented. Index Terms-CMOS multipliers, low noise design, low voltage circuits, multipliers.
|Number of pages||14|
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|Publication status||Published - 1998|
Bibliographical noteFunding Information:
Manuscript received April 11, 1997; revised August 14, 1998. This work was supported in part by the Mixed-Signal Group, Texas Instruments. This paper was recommended by Associate Editor F. Larsen. G. Han is with the Department of Electronic Engineering, Yonsei University, Seoul, Korea. E. Sánchez-Sincencio is with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128 USA (e-mail: email@example.com). Publisher Item Identifier S 1057-7130(98)09978-9.
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering