In parallel-architecture turbo codes, the constituent interleavers must avoid memory collision. This paper proposes a collision-free interleaver structure composed of a Latin square (LS) and pre-designed interleavers. Our proposed interleavers can be easily optimized for various information block sizes and for various degrees of parallelism. Their performances were evaluated by computer simulation.
Bibliographical noteFunding Information:
Manuscript received August 27, 2007. The associate editor coordinating the review of this letter and approving it for publication was D. Tuninetti. Support for this work was provided in part by Samsung Electronics under the project on 4G wireless communication systems. D.-S. Kim and H.-Y. Song are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea. H.-Y. Oh is with Samsung Electronics Co. Suwon, Korea (e-mail: email@example.com). Digital Object Identifier 10.1109/LCOMM.2008.071423.
All Science Journal Classification (ASJC) codes
- Modelling and Simulation
- Computer Science Applications
- Electrical and Electronic Engineering