Comparative analysis of 1:1:2 and 1:2:2 FinFET SRAM bit-cell using assist circuit

Kyuman Kang, Hanwool Jeong, Junha Lee, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Read and write yields of 6σ are achieved in 1:1:2 and 1:2:2 FinFET SRAM bit-cells using a negative bit-line write assist circuit and a suppressed word-line read assist circuit, respectively. These two bit-cells are compared in terms of read delay and leakage current. In spite of a smaller cell current, 1:1:2 bit-cell achieves 27.7% smaller read delay than 1:2:2 bit-cell due to a smaller bit-line capacitance. 1:1:2 bit-cell has a smaller leakage current due to the smaller fin number of pass gate transistors, but the difference is just 0.5% because of a larger Vth variation.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages35-38
Number of pages4
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Publication series

NameISOCC 2013 - 2013 International SoC Design Conference

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Kang, K., Jeong, H., Lee, J., & Jung, S. O. (2013). Comparative analysis of 1:1:2 and 1:2:2 FinFET SRAM bit-cell using assist circuit. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 35-38). [6863979] (ISOCC 2013 - 2013 International SoC Design Conference). IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863979