Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register

Jeongyong Sim, Sunghwan Joo, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents comparative analysis of digital STDP learning circuits designed using counter and shift register for spiking neural network (SNN). In addition, it is possible for the implemented STDP learning circuits to operate when two or more spikes occur at the same time. The conventional Von Neumann architecture has limitations such as speed bottleneck because the deep learning requires a lot of parallel data processing. In order to solve this problem, the researches on SNN similar to the human neural network have been widely performed. In this paper, the unsupervised spike-timing-dependent-plasticity (STDP) circuits designed for SNN system are studied. The circuits are implemented on a Kintex Ultra Scale FPGA. The implemented counter based STDP learning circuit consumes 1.6 times less power than the shift register based STDP, and uses 73.1% and 78.7% less LUTs and FFs than the shift register based circuit, respectively.

Original languageEnglish
Title of host publication34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728132716
DOIs
Publication statusPublished - 2019 Jun
Event34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 - JeJu, Korea, Republic of
Duration: 2019 Jun 232019 Jun 26

Publication series

Name34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019

Conference

Conference34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
CountryKorea, Republic of
CityJeJu
Period19/6/2319/6/26

Fingerprint

Shift registers
Plasticity
Networks (circuits)
Neural networks
Field programmable gate arrays (FPGA)

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Sim, J., Joo, S., & Jung, S. O. (2019). Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register. In 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 [8793424] (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC.2019.8793424
Sim, Jeongyong ; Joo, Sunghwan ; Jung, Seong Ook. / Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register. 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).
@inproceedings{5f74ac6f962f41b7a41bdda58924dee6,
title = "Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register",
abstract = "This paper presents comparative analysis of digital STDP learning circuits designed using counter and shift register for spiking neural network (SNN). In addition, it is possible for the implemented STDP learning circuits to operate when two or more spikes occur at the same time. The conventional Von Neumann architecture has limitations such as speed bottleneck because the deep learning requires a lot of parallel data processing. In order to solve this problem, the researches on SNN similar to the human neural network have been widely performed. In this paper, the unsupervised spike-timing-dependent-plasticity (STDP) circuits designed for SNN system are studied. The circuits are implemented on a Kintex Ultra Scale FPGA. The implemented counter based STDP learning circuit consumes 1.6 times less power than the shift register based STDP, and uses 73.1{\%} and 78.7{\%} less LUTs and FFs than the shift register based circuit, respectively.",
author = "Jeongyong Sim and Sunghwan Joo and Jung, {Seong Ook}",
year = "2019",
month = "6",
doi = "10.1109/ITC-CSCC.2019.8793424",
language = "English",
series = "34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019",
address = "United States",

}

Sim, J, Joo, S & Jung, SO 2019, Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register. in 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019., 8793424, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019, Institute of Electrical and Electronics Engineers Inc., 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019, JeJu, Korea, Republic of, 19/6/23. https://doi.org/10.1109/ITC-CSCC.2019.8793424

Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register. / Sim, Jeongyong; Joo, Sunghwan; Jung, Seong Ook.

34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8793424 (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register

AU - Sim, Jeongyong

AU - Joo, Sunghwan

AU - Jung, Seong Ook

PY - 2019/6

Y1 - 2019/6

N2 - This paper presents comparative analysis of digital STDP learning circuits designed using counter and shift register for spiking neural network (SNN). In addition, it is possible for the implemented STDP learning circuits to operate when two or more spikes occur at the same time. The conventional Von Neumann architecture has limitations such as speed bottleneck because the deep learning requires a lot of parallel data processing. In order to solve this problem, the researches on SNN similar to the human neural network have been widely performed. In this paper, the unsupervised spike-timing-dependent-plasticity (STDP) circuits designed for SNN system are studied. The circuits are implemented on a Kintex Ultra Scale FPGA. The implemented counter based STDP learning circuit consumes 1.6 times less power than the shift register based STDP, and uses 73.1% and 78.7% less LUTs and FFs than the shift register based circuit, respectively.

AB - This paper presents comparative analysis of digital STDP learning circuits designed using counter and shift register for spiking neural network (SNN). In addition, it is possible for the implemented STDP learning circuits to operate when two or more spikes occur at the same time. The conventional Von Neumann architecture has limitations such as speed bottleneck because the deep learning requires a lot of parallel data processing. In order to solve this problem, the researches on SNN similar to the human neural network have been widely performed. In this paper, the unsupervised spike-timing-dependent-plasticity (STDP) circuits designed for SNN system are studied. The circuits are implemented on a Kintex Ultra Scale FPGA. The implemented counter based STDP learning circuit consumes 1.6 times less power than the shift register based STDP, and uses 73.1% and 78.7% less LUTs and FFs than the shift register based circuit, respectively.

UR - http://www.scopus.com/inward/record.url?scp=85071453837&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85071453837&partnerID=8YFLogxK

U2 - 10.1109/ITC-CSCC.2019.8793424

DO - 10.1109/ITC-CSCC.2019.8793424

M3 - Conference contribution

AN - SCOPUS:85071453837

T3 - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019

BT - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Sim J, Joo S, Jung SO. Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register. In 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8793424. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019). https://doi.org/10.1109/ITC-CSCC.2019.8793424