Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register

Jeongyong Sim, Sunghwan Joo, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents comparative analysis of digital STDP learning circuits designed using counter and shift register for spiking neural network (SNN). In addition, it is possible for the implemented STDP learning circuits to operate when two or more spikes occur at the same time. The conventional Von Neumann architecture has limitations such as speed bottleneck because the deep learning requires a lot of parallel data processing. In order to solve this problem, the researches on SNN similar to the human neural network have been widely performed. In this paper, the unsupervised spike-timing-dependent-plasticity (STDP) circuits designed for SNN system are studied. The circuits are implemented on a Kintex Ultra Scale FPGA. The implemented counter based STDP learning circuit consumes 1.6 times less power than the shift register based STDP, and uses 73.1% and 78.7% less LUTs and FFs than the shift register based circuit, respectively.

Original languageEnglish
Title of host publication34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728132716
DOIs
Publication statusPublished - 2019 Jun
Event34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 - JeJu, Korea, Republic of
Duration: 2019 Jun 232019 Jun 26

Publication series

Name34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019

Conference

Conference34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
CountryKorea, Republic of
CityJeJu
Period19/6/2319/6/26

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture

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  • Cite this

    Sim, J., Joo, S., & Jung, S. O. (2019). Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register. In 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019 [8793424] (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC.2019.8793424