The authors report on the electrical reliabilities of poly-4-vinyl phenol (PVP) and SiO2 gate dielectrics for pentacene thin-film transistors (TFTs). SiO2 films were grown by dry oxidation and PVP films were prepared by spin coating and subsequent cross-linking at 175°C for 15 min. The pentacene TFTs with the PVP cured for 15 min exhibited a large hysteresis and an abnormal drain-current increase under a gate bias stress over time, while the other TFT with SiO2 displayed a small hysteresis but its drain current decreases with time. The hysteresis behaviors induced by PVP and SiO2 were opposite to each other in the gate bias swing direction, due to the difference in hysteresis mechanism between the two types of TFTs. Comparing their hysteresis behavior, the authors fabricated a far more reliable pentacene TFT with PVP by extending the PVP curing time to 1 h. Our improved device with PVP exhibited no hysteresis and persistent toughness to the gate bias stress.
Bibliographical noteFunding Information:
The authors are very appreciative of the financial support from KOSEF (Program No. M1-0214-00-0228) and LG Philips LCD Co. (project year 2005). They also acknowledge the support from Brain Korea 21 Project. One of the authors (J.H.K.) acknowledges financial support from the Electron Spin Science Center at Postech, funded by KOSEF/MOST.
All Science Journal Classification (ASJC) codes
- Physics and Astronomy (miscellaneous)