Low power circuit is an important concern for portable and battery operated applications. An attractive method to achieve low power consumption is supply voltage scaling. However, lowering the supply voltage causes a problem of stability in circuit, especially a static random access memory (SRAM). Since the SRAM occupies a large portion of the system-on-a-chip (SoC), the SRAM cell is typically designed using very small transistors for high integration, which causes the large mismatch between transistors in the SRAM cell. Thus, as supply voltage scales down, the static noise margin (SNM) of the 6T SRAM can limit the supply voltage scaling. The stability of read operation is especially sensitive to voltage scaling. To deal with these problems, recently proposed SRAM cells decouple the storage node from the bitline. In this paper, we analyze recently proposed SRAM cells for low voltage operation using 22 nm FinFET model.