Abstract
With technology scaling, reliability against soft errors is becoming an important design concern for modern embedded systems. To avoid the high cost and performance overheads of full protection techniques, several researches have therefore turned their focus to selective protection techniques. This increases the need to accurately identify the most vulnerable components or instructions in a system. In this paper, we analyze the vulnerability of a system from both the hardware and software perspectives through intensive fault injection trials. From the hardware perspective, we find the most vulnerable hardware components by calculating component-wise failure rates. From the software perspective, we identify the most vulnerable instructions by using the novel root cause instruction analysis. With our results, we show that it is possible to reduce the failure rate of a system to only 12.40% with minimal protection.
| Original language | English |
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| Title of host publication | Proceedings - 2021 IEEE 39th International Conference on Computer Design, ICCD 2021 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 204-207 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781665432191 |
| DOIs | |
| Publication status | Published - 2021 |
| Event | 39th IEEE International Conference on Computer Design, ICCD 2021 - Virtual, Online, United States Duration: 2021 Oct 24 → 2021 Oct 27 |
Publication series
| Name | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
|---|---|
| Volume | 2021-October |
| ISSN (Print) | 1063-6404 |
Conference
| Conference | 39th IEEE International Conference on Computer Design, ICCD 2021 |
|---|---|
| Country/Territory | United States |
| City | Virtual, Online |
| Period | 21/10/24 → 21/10/27 |
Bibliographical note
Funding Information:This work was partially supported by funding from National Science Foundation Grants No. CNS 1525855, CPS 1646235, CCF 1723476 - the NSF/Intel joint research center for Computer Assisted Programming for Heterogeneous Architectures (CAPA), 2014-3-00035 (High Performance and Scalable Manycore Operating System, IITP, MSIT), and Samsung Electronics Co., Ltd(FOUNDRY-202108DD007F).
Publisher Copyright:
© 2021 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering