Simultaneous switching noise (SSN) is a phenomenon with adverse and severe effects when a large number of high speed chip drivers switch simultaneously causing a large amount of current to be injected into the power distribution grid. The effects of SSN are manifested in a variety of transient and permanent system malfunctions including the appearance of undesirable glitches on what should otherwise be quiet signal lines and the flipping of state bits in registers and memories. Current approaches for dealing with SSN are largely ad hoc, relying primarily on the ability of expert designers to postulate worst-case scenarios for the occurrence of SSN-related errors and to analyze these scenarios using pessimistic estimates of packaging parasitics. This paper takes a first step toward evolving a systematic methodology for modeling and analysis of SSN in printed circuit boards (PCB's). The presented methodology adopts a combination of macro- and micro-models which allow for a system level treatment of the problem without losing the necessary detailed descriptions of the power/ground planes, the signal traces and the vertical interconnections through vias or plated holes. This approach has been applied to a variety of PCB structures and has allowed for an effective characterization of switching noise and a comprehensive understanding of its effects on PCB performance.
|Number of pages||11|
|Journal||IEEE Transactions on Components Packaging and Manufacturing Technology Part A|
|Publication status||Published - 1997 Mar|
Bibliographical noteFunding Information:
Manuscript received April 1, 1996; revised November 21, 1996. This work was funded in part by a Grant from the Intel Corporation. J.-G. Yook, V. Chandramouli, L. P. B. Katehi, and K. A. Sakallah are with the Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI 48109-2122 USA. T. R. Arabi and T. A. Schreyer are with the Intel Corporation. Publisher Item Identifier S 1070-9886(97)01830-1.
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