Computationally efficient sub-module selection scheme for voltage balancing controller of modular multilevel converter

G. T. Son, K. Hur, J. W. Park, S. T. Baek, U. H. Lee, Y. H. Chung

Research output: Contribution to conferencePaperpeer-review

Abstract

Modular multilevel converter (MMC) type topology is considered an enabling technology for expanding the voltage sourced converter (VSC) applications and thus providing its operational benefits with low switching power loss comparable to that of the conventional thyristor-based line commutated converters. However, due to its inherent topological and consequently control complexity, computational efficiency of the algorithms for fully simulating and then implementing the features of MMC are always pursued. MMC uses a stack of identical converter sub-modules, providing a step in the multilevel waveform, and the number of sub-modules may increase to more than 200 for the high power applications. Selection of the sub-modules set to be switched in or out, thus controlling and balancing the capacitor voltage for realizing the best performance at each control instant, may be the most crucial but time-consuming functions as well. Implementation steps of these functions are briefly discussed below: Generate reference signals for determining how many sub-modules in total are to be in the on-state condition at each control instant. This is called modulation process. Next select the sub-modules to be in. Note again that this process is for controlling the capacitor voltage of individual sub-modules. By balancing the capacitor voltage of each sub-module, it is possible to optimally utilize the stored energy and evenly distribute power losses to the installed electrical devices while avoiding concentration of thermal stress on specific sub-modules, which harmfully affects the life span of each submodule and the reliability of the MMC. Prior research efforts for designing voltage balancing controller have relied on sorting algorithm: individual capacitor voltages are first measured and are then sorted by their magnitudes. In case of positive arm current, the sub-module with the lowest voltage level is selected to charge its capacitor. In case of negative arm current, the sub-module with the highest voltage is selected to supply the output voltage level. This may be a straightforward way for selecting the sub-modules. However, as the number of sub-module increases for high voltage applications, the computational intensity to sort the capacitors increases: Note that it may require more than 200 sub-modules for the HVDC system and heavy computation should be a great challenge. Two representative sorting algorithms are considered in this study, i.e., bubble and quick sorting algorithms. Bubble sorting method takes computational time in the order of O(n2) theoretically. Quick sort requires computational time of O(nlogn) on average. For the state-of-the-art electromagnetic transient simulation methods, mostly based on the Norton Equivalent current source and conductance, these sorting algorithms must be a significant bottleneck in the simulation. Thus, our study presents a computationally efficient strategy for selecting the sub-modules. It is based on the analytical understanding of the change in the on-state condition of the MMC sub-module. All the possible operating modes of the sub-module has been investigated and only a single change of on-state condition of a sub-module is required to generate signals for the next control instant. This algorithm takes computation time of O(n), which can drastically reduce the simulation time. The computational efficiency and accuracy of the proposed algorithms have been demonstrated for typical MMC systems with reference to the existing sorting-based schemes by varying the number of sub-modules. In addition, system performances such as power dissipation from the switching elements and voltage variation from sub-sub-module capacitor have been investigated. The simulation results reveal that the proposed method reduces the computation efforts dramatically without compromising the system performance.

Original languageEnglish
Publication statusPublished - 2012
Event44th International Conference on Large High Voltage Electric Systems 2012 - Paris, France
Duration: 2012 Aug 262012 Aug 31

Other

Other44th International Conference on Large High Voltage Electric Systems 2012
CountryFrance
CityParis
Period12/8/2612/8/31

All Science Journal Classification (ASJC) codes

  • Energy Engineering and Power Technology
  • Fuel Technology

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