Cooperative cache system: A low power cache system for embedded processors

Gi Ho Park, Kil Whan Lee, Tack-Don Han, Shin-Dug Kim

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 μm 4-metal process technology.

Original languageEnglish
Pages (from-to)708-717
Number of pages10
JournalIEICE Transactions on Electronics
VolumeE90-C
Issue number4
DOIs
Publication statusPublished - 2007 Jan 1

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Electric power utilization
Electronic equipment
Metals

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

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Cooperative cache system : A low power cache system for embedded processors. / Park, Gi Ho; Lee, Kil Whan; Han, Tack-Don; Kim, Shin-Dug.

In: IEICE Transactions on Electronics, Vol. E90-C, No. 4, 01.01.2007, p. 708-717.

Research output: Contribution to journalArticle

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