Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM

Sara Choi, Taehui Na, Jisu Kim, Jung Pill Kim, Seung H. Kang, Seong Ook Jung

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34% for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.

Original languageEnglish
Article number7434047
Pages (from-to)2851-2860
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number9
DOIs
Publication statusPublished - 2016 Sep

Fingerprint

Torque
Data storage equipment
Electric potential
Networks (circuits)
Temperature
Scalability
Degradation
Industry

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Choi, Sara ; Na, Taehui ; Kim, Jisu ; Kim, Jung Pill ; Kang, Seung H. ; Jung, Seong Ook. / Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016 ; Vol. 24, No. 9. pp. 2851-2860.
@article{a98f5932ab9346a898d9bfd3baa63f0e,
title = "Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM",
abstract = "As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34{\%} for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.",
author = "Sara Choi and Taehui Na and Jisu Kim and Kim, {Jung Pill} and Kang, {Seung H.} and Jung, {Seong Ook}",
year = "2016",
month = "9",
doi = "10.1109/TVLSI.2016.2532878",
language = "English",
volume = "24",
pages = "2851--2860",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. / Choi, Sara; Na, Taehui; Kim, Jisu; Kim, Jung Pill; Kang, Seung H.; Jung, Seong Ook.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 9, 7434047, 09.2016, p. 2851-2860.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM

AU - Choi, Sara

AU - Na, Taehui

AU - Kim, Jisu

AU - Kim, Jung Pill

AU - Kang, Seung H.

AU - Jung, Seong Ook

PY - 2016/9

Y1 - 2016/9

N2 - As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34% for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.

AB - As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34% for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.

UR - http://www.scopus.com/inward/record.url?scp=84960982257&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84960982257&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2016.2532878

DO - 10.1109/TVLSI.2016.2532878

M3 - Article

AN - SCOPUS:84960982257

VL - 24

SP - 2851

EP - 2860

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 9

M1 - 7434047

ER -