As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34% for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.
|Number of pages||10|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2016 Sep|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering