Cost/performance trade-off in floating-point unit design for 3D geometry processor

Cheol Ho Jeong; Woo Chan Park; Tack Don Dan; Shin Dug Kim

doi:10.1109/APASIC.1999.824039

Cost/performance trade-off in floating-point unit design for 3D geometry processor

Cheol Ho Jeong, Woo Chan Park, Tack Don Dan, Shin Dug Kim

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	104-107
Number of pages	4
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824039
Publication status	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 1999 Aug 23 → 1999 Aug 25

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Other

Other	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	99/8/23 → 99/8/25

Bibliographical note

Publisher Copyright:
© 1999 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/APASIC.1999.824039

Cite this

Jeong, C. H., Park, W. C., Dan, T. D., & Kim, S. D. (1999). Cost/performance trade-off in floating-point unit design for 3D geometry processor. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 104-107). [824039] (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824039

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title = "Cost/performance trade-off in floating-point unit design for 3D geometry processor",

abstract = "Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.",

author = "Jeong, {Cheol Ho} and Park, {Woo Chan} and Dan, {Tack Don} and Kim, {Shin Dug}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",

year = "1999",

doi = "10.1109/APASIC.1999.824039",

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series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

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Jeong, CH, Park, WC, Dan, TD & Kim, SD 1999, Cost/performance trade-off in floating-point unit design for 3D geometry processor. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824039, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 104-107, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 99/8/23. https://doi.org/10.1109/APASIC.1999.824039

Cost/performance trade-off in floating-point unit design for 3D geometry processor. / Jeong, Cheol Ho; Park, Woo Chan; Dan, Tack Don et al.

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 104-107 824039 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.

AB - Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.

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Cost/performance trade-off in floating-point unit design for 3D geometry processor

Abstract

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Bibliographical note

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