Cost/performance trade-off in floating-point unit design for 3D geometry processor

Cheol Ho Jeong, Woo Chan Park, Tack Don Dan, Shin Dug Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages104-107
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
Publication statusPublished - 1999 Jan 1
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 1999 Aug 231999 Aug 25

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Other

Other1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
CountryKorea, Republic of
CitySeoul
Period99/8/2399/8/25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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    Jeong, C. H., Park, W. C., Dan, T. D., & Kim, S. D. (1999). Cost/performance trade-off in floating-point unit design for 3D geometry processor. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 104-107). [824039] (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824039