TY - GEN
T1 - Cost/performance trade-off in floating-point unit design for 3D geometry processor
AU - Jeong, Cheol Ho
AU - Park, Woo Chan
AU - Dan, Tack Don
AU - Kim, Shin Dug
N1 - Publisher Copyright:
© 1999 IEEE.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 1999
Y1 - 1999
N2 - Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.
AB - Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.
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U2 - 10.1109/APASIC.1999.824039
DO - 10.1109/APASIC.1999.824039
M3 - Conference contribution
AN - SCOPUS:27944442332
SN - 0780357051
SN - 9780780357051
T3 - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
SP - 104
EP - 107
BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Y2 - 23 August 1999 through 25 August 1999
ER -