Coupling-aware minimum delay optimization for domino logic circuits

Ki Wook Kim, Seong Ook Jung, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Minimum delay associated with the hold time requirement is a concern to circuit designers, since race-through hazards are inherent to any multiple clock organization or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the min-delay path failure through coupling-induced speedup. To tackle the min-delay problem for domino logic, we propose a min-delay optimization algorithm considering coupling effects. Experimental results indicate that our algorithm yields significant increase of min-delay without incurring max-delay violation.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
PublisherIEEE Computer Society
Pages371-374
Number of pages4
ISBN (Print)0780366859, 9780780366855
Publication statusPublished - 2001 Jan 1
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume5

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01/5/601/5/9

Fingerprint

Logic circuits
Clocks
Hazards
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, K. W., Jung, S. O., & Kang, S. M. (2001). Coupling-aware minimum delay optimization for domino logic circuits. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 371-374). [922062] (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 5). IEEE Computer Society.
Kim, Ki Wook ; Jung, Seong Ook ; Kang, Sung Mo. / Coupling-aware minimum delay optimization for domino logic circuits. ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, 2001. pp. 371-374 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings).
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Kim, KW, Jung, SO & Kang, SM 2001, Coupling-aware minimum delay optimization for domino logic circuits. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922062, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 5, IEEE Computer Society, pp. 371-374, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 01/5/6.

Coupling-aware minimum delay optimization for domino logic circuits. / Kim, Ki Wook; Jung, Seong Ook; Kang, Sung Mo.

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, 2001. p. 371-374 922062 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 5).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Kim KW, Jung SO, Kang SM. Coupling-aware minimum delay optimization for domino logic circuits. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society. 2001. p. 371-374. 922062. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings).