@inproceedings{525b1e9183884a1c9365fba8e1a9a843,
title = "Coupling-aware minimum delay optimization for domino logic circuits",
abstract = "Minimum delay associated with the hold time requirement is a concern to circuit designers, since race-through hazards are inherent to any multiple clock organization or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the min-delay path failure through coupling-induced speedup. To tackle the min-delay problem for domino logic, we propose a min-delay optimization algorithm considering coupling effects. Experimental results indicate that our algorithm yields significant increase of min-delay without incurring max-delay violation.",
author = "Kim, {Ki Wook} and Jung, {Seong Ook} and Kang, {Sung Mo}",
year = "2001",
doi = "10.1109/iscas.2001.922062",
language = "English",
isbn = "0780366859",
series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",
publisher = "IEEE Computer Society",
pages = "371--374",
booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",
address = "United States",
note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",
}