Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

Ki Wook Kim; Seong Ook Jung; Taewhan Kim; Prashant Saxena; C. L. Liu; Sung Mo Kang

doi:10.1109/TVLSI.2003.817111

Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

Ki Wook Kim, Seong Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual V_t technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low V_t is applied properly.

Original language	English
Pages (from-to)	879-887
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	11
Issue number	5
DOIs	https://doi.org/10.1109/TVLSI.2003.817111
Publication status	Published - 2003 Oct

Bibliographical note

Funding Information:
Manuscript received February 19, 2002; revised January 13, 2003. The work of T. Kim was supported by the Korea Science and Engineering Foundation (KOSEF) under the Advanced Information Technology Research Center (AITrc). K.-W. Kim is with Brocade Communications Systems Inc., San Jose, CA 95110 USA (e-mail: kimk@brocade.com). S.-O. Jung is with T-RAM Inc., San Jose, CA 95134 USA (e-mail: sojung@tram.com). T. Kim is with Department of Electrical Engineering and Computer Science and AITrc, Korea Advanced Institute of Science and Technology (KAIST), Dae-jeon, 305-701 Korea (e-mail: tkim@cs.kaist.ac.kr). P. Saxena is with Intel Corporation, Hillsboro, OR 97123 USA (e-mail: prashant.saxena@intel.com). C. L. Liu is with National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C. S.-M. S. Kang is with School of Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064 USA. Digital Object Identifier 10.1109/TVLSI.2003.817111

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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Cite this

@article{3e846f2d87d54fd5b501022c4d0b977d,

title = "Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique",

abstract = "Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.",

author = "Kim, {Ki Wook} and Jung, {Seong Ook} and Taewhan Kim and Prashant Saxena and Liu, {C. L.} and Kang, {Sung Mo}",

note = "Funding Information: Manuscript received February 19, 2002; revised January 13, 2003. The work of T. Kim was supported by the Korea Science and Engineering Foundation (KOSEF) under the Advanced Information Technology Research Center (AITrc). K.-W. Kim is with Brocade Communications Systems Inc., San Jose, CA 95110 USA (e-mail: kimk@brocade.com). S.-O. Jung is with T-RAM Inc., San Jose, CA 95134 USA (e-mail: sojung@tram.com). T. Kim is with Department of Electrical Engineering and Computer Science and AITrc, Korea Advanced Institute of Science and Technology (KAIST), Dae-jeon, 305-701 Korea (e-mail: tkim@cs.kaist.ac.kr). P. Saxena is with Intel Corporation, Hillsboro, OR 97123 USA (e-mail: prashant.saxena@intel.com). C. L. Liu is with National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C. S.-M. S. Kang is with School of Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064 USA. Digital Object Identifier 10.1109/TVLSI.2003.817111",

year = "2003",

month = oct,

doi = "10.1109/TVLSI.2003.817111",

language = "English",

volume = "11",

pages = "879--887",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

AU - Kim, Ki Wook

AU - Jung, Seong Ook

AU - Kim, Taewhan

AU - Saxena, Prashant

AU - Liu, C. L.

AU - Kang, Sung Mo

N1 - Funding Information: Manuscript received February 19, 2002; revised January 13, 2003. The work of T. Kim was supported by the Korea Science and Engineering Foundation (KOSEF) under the Advanced Information Technology Research Center (AITrc). K.-W. Kim is with Brocade Communications Systems Inc., San Jose, CA 95110 USA (e-mail: kimk@brocade.com). S.-O. Jung is with T-RAM Inc., San Jose, CA 95134 USA (e-mail: sojung@tram.com). T. Kim is with Department of Electrical Engineering and Computer Science and AITrc, Korea Advanced Institute of Science and Technology (KAIST), Dae-jeon, 305-701 Korea (e-mail: tkim@cs.kaist.ac.kr). P. Saxena is with Intel Corporation, Hillsboro, OR 97123 USA (e-mail: prashant.saxena@intel.com). C. L. Liu is with National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C. S.-M. S. Kang is with School of Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064 USA. Digital Object Identifier 10.1109/TVLSI.2003.817111

PY - 2003/10

Y1 - 2003/10

N2 - Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.

AB - Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.

UR - http://www.scopus.com/inward/record.url?scp=0142227162&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0142227162&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2003.817111

DO - 10.1109/TVLSI.2003.817111

M3 - Article

AN - SCOPUS:0142227162

VL - 11

SP - 879

EP - 887

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 5

ER -

Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

Abstract

Bibliographical note

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