Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

Ki Wook Kim; Seong Ook Jung; Taewhan Kim; Prashant Saxena; C. L. Liu; Sung Mo Kang

doi:10.1109/TVLSI.2003.817111

Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

Ki Wook Kim, Seong Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article

5 Citations (Scopus)

Abstract

Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual V_t technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low V_t is applied properly.

Original language	English
Pages (from-to)	879-887
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	11
Issue number	5
DOIs	https://doi.org/10.1109/TVLSI.2003.817111
Publication status	Published - 2003 Oct 1

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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Kim, K. W., Jung, S. O., Kim, T., Saxena, P., Liu, C. L., & Kang, S. M. (2003). Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(5), 879-887. https://doi.org/10.1109/TVLSI.2003.817111

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