Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

Ki Wook Kim, Seong Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, Sung Mo Kang

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.

Original languageEnglish
Pages (from-to)879-887
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number5
DOIs
Publication statusPublished - 2003 Oct 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique'. Together they form a unique fingerprint.

  • Cite this