Abstract
Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.
| Original language | English |
|---|---|
| Pages (from-to) | 879-887 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 11 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2003 Oct 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
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Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique. / Kim, Ki Wook; Jung, Seongook; Kim, Taewhan; Saxena, Prashant; Liu, C. L.; Kang, Sung Mo.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 5, 01.10.2003, p. 879-887.Research output: Contribution to journal › Article
TY - JOUR
T1 - Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique
AU - Kim, Ki Wook
AU - Jung, Seongook
AU - Kim, Taewhan
AU - Saxena, Prashant
AU - Liu, C. L.
AU - Kang, Sung Mo
PY - 2003/10/1
Y1 - 2003/10/1
N2 - Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.
AB - Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.
UR - http://www.scopus.com/inward/record.url?scp=0142227162&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0142227162&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2003.817111
DO - 10.1109/TVLSI.2003.817111
M3 - Article
AN - SCOPUS:0142227162
VL - 11
SP - 879
EP - 887
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 5
ER -