Coupling Delay Optimization by Temporal Decorrelation Using Dual Threshold Voltage Technique

Ki Wook Kim, Seong Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, Sung Mo Kang

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

Coupling effect due to line-to-Iine capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.

Original languageEnglish
Pages (from-to)879-887
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number5
DOIs
Publication statusPublished - 2003 Oct

Bibliographical note

Funding Information:
Manuscript received February 19, 2002; revised January 13, 2003. The work of T. Kim was supported by the Korea Science and Engineering Foundation (KOSEF) under the Advanced Information Technology Research Center (AITrc). K.-W. Kim is with Brocade Communications Systems Inc., San Jose, CA 95110 USA (e-mail: kimk@brocade.com). S.-O. Jung is with T-RAM Inc., San Jose, CA 95134 USA (e-mail: sojung@tram.com). T. Kim is with Department of Electrical Engineering and Computer Science and AITrc, Korea Advanced Institute of Science and Technology (KAIST), Dae-jeon, 305-701 Korea (e-mail: tkim@cs.kaist.ac.kr). P. Saxena is with Intel Corporation, Hillsboro, OR 97123 USA (e-mail: prashant.saxena@intel.com). C. L. Liu is with National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C. S.-M. S. Kang is with School of Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064 USA. Digital Object Identifier 10.1109/TVLSI.2003.817111

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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