I/O performance plays a critical role in the overall performance of modern servers. The emergence of ultra high-speed I/O devices makes the data movement between processors, main memory, and devices a major performance bottleneck. Conventionally, the main memory is used as an intermediate buffer between the processor and I/O devices and I/O devices cannot directly access processor side caches. Data Direct I/O (DDIO) technology aims to reduce the memory bandwidth utilization by enabling the I/O devices to leverage Last Level Cache (LLC) as the intermediate buffer. Our experimental results show that DDIO can completely eliminate memory bandwidth utilization while running network-or storage-intensive applications. However, when modeling the I/O subsystem using architectural simulators, DDIO is often ignored, which can result in inaccurate assessments about the I/O and memory sub system of emerging and future large-scale computer systems. In this paper, we provide a detailed background on DDIO technology in Intel server processors. Then we present our cycle-accurate I/O subsystem model in gem5 simulator that can be configured to model DDIO. We verify our model against baseline gem5 and validate it by comparing its results against a physical computer system.
|Title of host publication||Proceedings - 2020 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||10|
|Publication status||Published - 2020 Aug|
|Event||2020 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020 - Boston, United States|
Duration: 2020 Aug 23 → 2020 Aug 25
|Name||Proceedings - 2020 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020|
|Conference||2020 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020|
|Period||20/8/23 → 20/8/25|
Bibliographical noteFunding Information:
VIII. ACKNOWLEDGMENTS We would like to thank the anonymous reviewers for their comments. We also thank Anil Vasudevan, Robert Blanken-ship, Bin Li and Charlie Tai, for their insightful feedback and technical support. This work is supported by funding from National Science Foundation (No. CNS-1705047).
© 2020 IEEE.
All Science Journal Classification (ASJC) codes
- Artificial Intelligence
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality