Data randomization scheme for endurance enhancement and interference mitigation of multilevel flash memory devices

Jaewon Cha, Sungho Kang

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

Original languageEnglish
Pages (from-to)166-169
Number of pages4
JournalETRI Journal
Volume35
Issue number1
DOIs
Publication statusPublished - 2013 Feb 1

Fingerprint

Flash memory
Durability
Data storage equipment
Bit error rate
Seed
Experiments

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

@article{eccaa955089841ae9775fe619d08e4c1,
title = "Data randomization scheme for endurance enhancement and interference mitigation of multilevel flash memory devices",
abstract = "In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86{\%} compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.",
author = "Jaewon Cha and Sungho Kang",
year = "2013",
month = "2",
day = "1",
doi = "10.4218/etrij.13.0212.0273",
language = "English",
volume = "35",
pages = "166--169",
journal = "ETRI Journal",
issn = "1225-6463",
publisher = "ETRI",
number = "1",

}

Data randomization scheme for endurance enhancement and interference mitigation of multilevel flash memory devices. / Cha, Jaewon; Kang, Sungho.

In: ETRI Journal, Vol. 35, No. 1, 01.02.2013, p. 166-169.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Data randomization scheme for endurance enhancement and interference mitigation of multilevel flash memory devices

AU - Cha, Jaewon

AU - Kang, Sungho

PY - 2013/2/1

Y1 - 2013/2/1

N2 - In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

AB - In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

UR - http://www.scopus.com/inward/record.url?scp=84873693297&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84873693297&partnerID=8YFLogxK

U2 - 10.4218/etrij.13.0212.0273

DO - 10.4218/etrij.13.0212.0273

M3 - Article

AN - SCOPUS:84873693297

VL - 35

SP - 166

EP - 169

JO - ETRI Journal

JF - ETRI Journal

SN - 1225-6463

IS - 1

ER -