Abstract
Only with a right schedule and a right topology layout, a graph algorithm can be efciently processed on GPUs. Existing GPU graph processing frameworks try to fnd an optimal schedule and topology layout for an algorithm via iterative search, but they fail to fnd the optimal confguration because their schedules and topology layouts are tightly coupled in their processing models. Moreover, their tightly coupled schedules and topology layouts make it diffcult for developers to extend the tuning space. To easily enlarge the tuning space of GPU graph processing, this work proposes a new GPU graph processing abstraction scheme that fully decouples schedules, topology layouts, and algorithms from each other with abstraction interfaces. Moreover, this work proposes GRAssembler, a new GPU graph processing framework that efciently integrates the decoupled schedule, topology layout, and algorithm without abstraction overhead. Thanks to the efcient decoupling and integration, GRAssembler increases the tuning space from 336 to 4,480 and achieves 30.4% higher performance on geomean average, compared to the state-of-the-art GPU graph processing framework.
Original language | English |
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Title of host publication | PACT 2022 - Proceedings of the 2022 International Conference on Parallel Architectures and Compilation Techniques |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 198-210 |
Number of pages | 13 |
ISBN (Electronic) | 9781450398688 |
DOIs | |
Publication status | Published - 2022 Oct 8 |
Event | 31st International Conference on Parallel Architectures and Compilation Techniques, PACT 2022 - Chicago, United States Duration: 2022 Oct 8 → 2022 Oct 10 |
Publication series
Name | Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT |
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ISSN (Print) | 1089-795X |
Conference
Conference | 31st International Conference on Parallel Architectures and Compilation Techniques, PACT 2022 |
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Country/Territory | United States |
City | Chicago |
Period | 22/10/8 → 22/10/10 |
Bibliographical note
Funding Information:We thank the anonymous reviewers for their valuable feedback. We also thank the CoreLab members for their support and feedback during this work. This work is supported by IITP-2020-0-01847, IITP-2020-0-01361, IITP-2021-0-00853, and IITP-2022-0-00050 through the Institute of Information and Communication Technology Planning and Evaluation (IITP) funded by the Ministry of Science and ICT. This work is also supported by Samsung Electronics. (Corresponding author: Hanjun Kim)
Publisher Copyright:
© 2022 Association for Computing Machinery.
All Science Journal Classification (ASJC) codes
- Software
- Theoretical Computer Science
- Hardware and Architecture