Decoupling the bias-stress-induced charge trapping in semiconductors and gate-dielectrics of organic transistors using a double stretched-exponential formula

Hyun Ho Choi, Moon Sung Kang, Min Kim, Haena Kim, Jeong Ho Cho, Kilwon Cho

Research output: Contribution to journalArticle

27 Citations (Scopus)

Abstract

A novel strategy for analyzing bias-stress effects in organic field-effect transistors (OFETs) based on a four-parameter double stretched-exponential formula is reported. The formula is obtained by modifying a traditional single stretched-exponential expression comprising two parameters (a characteristic time and a stretched-exponential factor) that describe the bias-stress effects. The expression yields two characteristic times and two stretched-exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer-side of the interface and the gate-dielectric layer-side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate-dielectric layer were varied systematically. It was found that the gate-dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias-stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self-assembled monolayer further widens the distribution of the activation energy for charge trapping in gate-dielectric layer-side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance. Double stretched-exponential formula enables the bias-stress-induced charge trapping in semiconductor and gate-dielectric layers in organic field-effect transistors to be separately described. The gate-dielectric layer is found to play a more critical role than the semiconductor layer in the bias-stress effects, possibly because the distribution of the activation energy for charge trapping in the gate-dielectric layer is wider than the semiconductor.

Original languageEnglish
Pages (from-to)690-696
Number of pages7
JournalAdvanced Functional Materials
Volume23
Issue number6
DOIs
Publication statusPublished - 2013 Feb 11

Fingerprint

Charge trapping
Gate dielectrics
decoupling
Transistors
transistors
trapping
Semiconductor materials
Organic field effect transistors
Activation energy
field effect transistors
activation energy
Self assembled monolayers
Physical properties
physical properties

All Science Journal Classification (ASJC) codes

  • Chemistry(all)
  • Materials Science(all)
  • Condensed Matter Physics

Cite this

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title = "Decoupling the bias-stress-induced charge trapping in semiconductors and gate-dielectrics of organic transistors using a double stretched-exponential formula",
abstract = "A novel strategy for analyzing bias-stress effects in organic field-effect transistors (OFETs) based on a four-parameter double stretched-exponential formula is reported. The formula is obtained by modifying a traditional single stretched-exponential expression comprising two parameters (a characteristic time and a stretched-exponential factor) that describe the bias-stress effects. The expression yields two characteristic times and two stretched-exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer-side of the interface and the gate-dielectric layer-side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate-dielectric layer were varied systematically. It was found that the gate-dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias-stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self-assembled monolayer further widens the distribution of the activation energy for charge trapping in gate-dielectric layer-side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance. Double stretched-exponential formula enables the bias-stress-induced charge trapping in semiconductor and gate-dielectric layers in organic field-effect transistors to be separately described. The gate-dielectric layer is found to play a more critical role than the semiconductor layer in the bias-stress effects, possibly because the distribution of the activation energy for charge trapping in the gate-dielectric layer is wider than the semiconductor.",
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Decoupling the bias-stress-induced charge trapping in semiconductors and gate-dielectrics of organic transistors using a double stretched-exponential formula. / Choi, Hyun Ho; Kang, Moon Sung; Kim, Min; Kim, Haena; Cho, Jeong Ho; Cho, Kilwon.

In: Advanced Functional Materials, Vol. 23, No. 6, 11.02.2013, p. 690-696.

Research output: Contribution to journalArticle

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T1 - Decoupling the bias-stress-induced charge trapping in semiconductors and gate-dielectrics of organic transistors using a double stretched-exponential formula

AU - Choi, Hyun Ho

AU - Kang, Moon Sung

AU - Kim, Min

AU - Kim, Haena

AU - Cho, Jeong Ho

AU - Cho, Kilwon

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Y1 - 2013/2/11

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AB - A novel strategy for analyzing bias-stress effects in organic field-effect transistors (OFETs) based on a four-parameter double stretched-exponential formula is reported. The formula is obtained by modifying a traditional single stretched-exponential expression comprising two parameters (a characteristic time and a stretched-exponential factor) that describe the bias-stress effects. The expression yields two characteristic times and two stretched-exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer-side of the interface and the gate-dielectric layer-side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate-dielectric layer were varied systematically. It was found that the gate-dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias-stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self-assembled monolayer further widens the distribution of the activation energy for charge trapping in gate-dielectric layer-side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance. Double stretched-exponential formula enables the bias-stress-induced charge trapping in semiconductor and gate-dielectric layers in organic field-effect transistors to be separately described. The gate-dielectric layer is found to play a more critical role than the semiconductor layer in the bias-stress effects, possibly because the distribution of the activation energy for charge trapping in the gate-dielectric layer is wider than the semiconductor.

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