TY - JOUR
T1 - Demonstration of high-performance PMOSFETs Using Si-Six Ge1-x-Si quantum wells with high-κ metal-gate stacks
AU - Majhi, Prashant
AU - Kalra, P.
AU - Harris, R.
AU - Choi, K. J.
AU - Heh, D.
AU - Oh, J.
AU - Kelly, D.
AU - Choi, R.
AU - Cho, B. J.
AU - Banerjee, S.
AU - Tsai, W.
AU - Tseng, H.
AU - Jammy, R.
PY - 2008/1
Y1 - 2008/1
N2 - Through a systematic approach, PMOSFETs with strained quantum wells (QWs) in the Si-Ge system exhibiting high performance and low off-state leakage currents comparable to optimized gate stacks on Si are demonstrated. The encouraging results are due to selectively depositing Si-Si(x)Ge(1-x)-Si heterostructure QWs, where it appears that the critical thickness requirements for these thin films based on the lattice constant mismatch are relaxed. Furthermore, the use of optimal advanced high-κ dielectric and metal-gate electrode helped realize the good device characteristics.
AB - Through a systematic approach, PMOSFETs with strained quantum wells (QWs) in the Si-Ge system exhibiting high performance and low off-state leakage currents comparable to optimized gate stacks on Si are demonstrated. The encouraging results are due to selectively depositing Si-Si(x)Ge(1-x)-Si heterostructure QWs, where it appears that the critical thickness requirements for these thin films based on the lattice constant mismatch are relaxed. Furthermore, the use of optimal advanced high-κ dielectric and metal-gate electrode helped realize the good device characteristics.
UR - http://www.scopus.com/inward/record.url?scp=37549024971&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=37549024971&partnerID=8YFLogxK
U2 - 10.1109/LED.2007.911987
DO - 10.1109/LED.2007.911987
M3 - Article
AN - SCOPUS:37549024971
VL - 29
SP - 99
EP - 101
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
SN - 0741-3106
IS - 1
ER -