Demonstration of high-performance PMOSFETs Using Si-Six Ge1-x-Si quantum wells with high-κ metal-gate stacks

Prashant Majhi, P. Kalra, R. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B. J. Cho, S. Banerjee, W. Tsai, H. Tseng, R. Jammy

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14 Citations (Scopus)

Abstract

Through a systematic approach, PMOSFETs with strained quantum wells (QWs) in the Si-Ge system exhibiting high performance and low off-state leakage currents comparable to optimized gate stacks on Si are demonstrated. The encouraging results are due to selectively depositing Si-Si(x)Ge(1-x)-Si heterostructure QWs, where it appears that the critical thickness requirements for these thin films based on the lattice constant mismatch are relaxed. Furthermore, the use of optimal advanced high-κ dielectric and metal-gate electrode helped realize the good device characteristics.

Original languageEnglish
Pages (from-to)99-101
Number of pages3
JournalIEEE Electron Device Letters
Volume29
Issue number1
DOIs
Publication statusPublished - 2008 Jan 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Majhi, P., Kalra, P., Harris, R., Choi, K. J., Heh, D., Oh, J., Kelly, D., Choi, R., Cho, B. J., Banerjee, S., Tsai, W., Tseng, H., & Jammy, R. (2008). Demonstration of high-performance PMOSFETs Using Si-Six Ge1-x-Si quantum wells with high-κ metal-gate stacks. IEEE Electron Device Letters, 29(1), 99-101. https://doi.org/10.1109/LED.2007.911987