Demonstration of Lg ∼ nm pMOSFETs with Si/Si0.25Ge0.75/Si channels, high Ion/Ioff (>5 × 104, and controlled short channel effects (SCEs)

Se Hoon Lee, Prashant Majhi, Jungwoo Oh, Barry Sassman, Chadwin Young, Anupama Bowonder, Wei Yip Loh, Kyu Jin Choi, Byung Jin Cho, Hi Deok Lee, Paul Kirsch, Harlan Rusty Harris, Wilman Tsai, Suman Datta, Hsing Huang Tseng, Sanjay K. Banerjee, Raj Jammy

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Abstract

High-performance sub-60 nm Si/SiGe (Ge: ∼ 75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high- κ/metal gate stacks with ∼1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length Lg devices demonstrate not only controlled short channel effects, but also an excellent on-off current (Ion /Ioof ratio (∼5 × 104 at 55-nm Lg. The intrinsic gate delay of these heterostructures is ∼3 ps at Ion/Ioff ∼ 104 OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short Lf devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

Original languageEnglish
Pages (from-to)1017-1020
Number of pages4
JournalIEEE Electron Device Letters
Volume29
Issue number9
DOIs
Publication statusPublished - 2008 Sep 5

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Lee, S. H., Majhi, P., Oh, J., Sassman, B., Young, C., Bowonder, A., Loh, W. Y., Choi, K. J., Cho, B. J., Lee, H. D., Kirsch, P., Harris, H. R., Tsai, W., Datta, S., Tseng, H. H., Banerjee, S. K., & Jammy, R. (2008). Demonstration of Lg ∼ nm pMOSFETs with Si/Si0.25Ge0.75/Si channels, high Ion/Ioff (>5 × 104, and controlled short channel effects (SCEs). IEEE Electron Device Letters, 29(9), 1017-1020. https://doi.org/10.1109/LED.2008.2002073