Abstract
Continuing demands for high degrees of Instruction Level Parallelism (ILP) require large dispatch queues in modern superscalar microprocessors. However, such large queues are inevitably accompanied by high circuit complexity which correspondingly limits the pipeline clock rates. This is due to the fact that most of today's designs are based upon a centralized dispatch queue which depends on globally broadcasting operations to wake up and select the ready instructions. As an alternative to this conventional design, we propose the design of hierarchically distributed dispatch queues, based on the access/execute decoupled architecture model. Simulation results based on 14 data intensive benchmarks show that our DDQ (Decoupled Dispatch Queues) design achieves performance comparable to a superscalar machine with a large dispatch queue. We also show that our DDQ can be designed with small-sized, distributed dispatch queues which consequently can be implemented with low hardware complexity and high clock rates.
| Original language | English |
|---|---|
| Title of host publication | Euro-Par 2006 Parallel Processing - 12th International Euro-Par Conference, Proceedings |
| Publisher | Springer Verlag |
| Pages | 485-494 |
| Number of pages | 10 |
| ISBN (Print) | 3540377832, 9783540377832 |
| Publication status | Published - 2006 Jan 1 |
| Event | 12th International Euro-Par Conference 2006 - Lisbon, Portugal Duration: 2006 Aug 28 → 2006 Sep 1 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 4128 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Other
| Other | 12th International Euro-Par Conference 2006 |
|---|---|
| Country | Portugal |
| City | Lisbon |
| Period | 06/8/28 → 06/9/1 |
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All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Computer Science(all)
Cite this
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Design and effectiveness of small-sized decoupled dispatch queues. / Ro, Won W.; Gaudiot, Jean Luc.
Euro-Par 2006 Parallel Processing - 12th International Euro-Par Conference, Proceedings. Springer Verlag, 2006. p. 485-494 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4128 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Design and effectiveness of small-sized decoupled dispatch queues
AU - Ro, Won W.
AU - Gaudiot, Jean Luc
PY - 2006/1/1
Y1 - 2006/1/1
N2 - Continuing demands for high degrees of Instruction Level Parallelism (ILP) require large dispatch queues in modern superscalar microprocessors. However, such large queues are inevitably accompanied by high circuit complexity which correspondingly limits the pipeline clock rates. This is due to the fact that most of today's designs are based upon a centralized dispatch queue which depends on globally broadcasting operations to wake up and select the ready instructions. As an alternative to this conventional design, we propose the design of hierarchically distributed dispatch queues, based on the access/execute decoupled architecture model. Simulation results based on 14 data intensive benchmarks show that our DDQ (Decoupled Dispatch Queues) design achieves performance comparable to a superscalar machine with a large dispatch queue. We also show that our DDQ can be designed with small-sized, distributed dispatch queues which consequently can be implemented with low hardware complexity and high clock rates.
AB - Continuing demands for high degrees of Instruction Level Parallelism (ILP) require large dispatch queues in modern superscalar microprocessors. However, such large queues are inevitably accompanied by high circuit complexity which correspondingly limits the pipeline clock rates. This is due to the fact that most of today's designs are based upon a centralized dispatch queue which depends on globally broadcasting operations to wake up and select the ready instructions. As an alternative to this conventional design, we propose the design of hierarchically distributed dispatch queues, based on the access/execute decoupled architecture model. Simulation results based on 14 data intensive benchmarks show that our DDQ (Decoupled Dispatch Queues) design achieves performance comparable to a superscalar machine with a large dispatch queue. We also show that our DDQ can be designed with small-sized, distributed dispatch queues which consequently can be implemented with low hardware complexity and high clock rates.
UR - http://www.scopus.com/inward/record.url?scp=33749998948&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33749998948&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33749998948
SN - 3540377832
SN - 9783540377832
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 485
EP - 494
BT - Euro-Par 2006 Parallel Processing - 12th International Euro-Par Conference, Proceedings
PB - Springer Verlag
ER -