Design and implementation of MIMO-OFDM baseband processor for high-speed wireless LANs

Yunho Jung, Jiho Kim, Seongjoo Lee, Hong Il Yoon, Jaeseok Kim

Research output: Contribution to journalArticle

32 Citations (Scopus)

Abstract

In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10% packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 ×3.9 mm2 using 0.18-μm CMOS process.

Original languageEnglish
Pages (from-to)631-635
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume54
Issue number7
DOIs
Publication statusPublished - 2007 Jul 7

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Local area networks
Orthogonal frequency division multiplexing
Wireless local area networks (WLAN)
Decoding
Signal to noise ratio
Transistors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10{\%} packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 ×3.9 mm2 using 0.18-μm CMOS process.",
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Design and implementation of MIMO-OFDM baseband processor for high-speed wireless LANs. / Jung, Yunho; Kim, Jiho; Lee, Seongjoo; Yoon, Hong Il; Kim, Jaeseok.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, No. 7, 07.07.2007, p. 631-635.

Research output: Contribution to journalArticle

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