In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10% packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 ×3.9 mm2 using 0.18-μm CMOS process.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2007 Jul 7|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering