Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs

Gaurav Kaushal, K. Subramanyam, Siva Nageswar Rao, G. Vidya, Radhika Ramya, Sadulla Shaik, H. Jeong, S. O. Jung, Ramesh Vaddi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.

Original languageEnglish
Title of host publicationISOCC 2014 - International SoC Design Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages32-33
Number of pages2
ISBN (Electronic)9781479951260
DOIs
Publication statusPublished - 2015 Apr 16
Event11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of
Duration: 2014 Nov 32014 Nov 6

Publication series

NameISOCC 2014 - International SoC Design Conference

Other

Other11th International SoC Design Conference, ISOCC 2014
CountryKorea, Republic of
CityJeju
Period14/11/314/11/6

Fingerprint

Digital circuits
Analog circuits
Benchmarking
Tunnels
Transistors
Field effect transistors
Networks (circuits)
Electric potential
Energy harvesting
Heavy ions
Energy utilization
Monitoring

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Kaushal, G., Subramanyam, K., Rao, S. N., Vidya, G., Ramya, R., Shaik, S., ... Vaddi, R. (2015). Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. In ISOCC 2014 - International SoC Design Conference (pp. 32-33). [7087570] (ISOCC 2014 - International SoC Design Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2014.7087570
Kaushal, Gaurav ; Subramanyam, K. ; Rao, Siva Nageswar ; Vidya, G. ; Ramya, Radhika ; Shaik, Sadulla ; Jeong, H. ; Jung, S. O. ; Vaddi, Ramesh. / Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 32-33 (ISOCC 2014 - International SoC Design Conference).
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abstract = "This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.",
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Kaushal, G, Subramanyam, K, Rao, SN, Vidya, G, Ramya, R, Shaik, S, Jeong, H, Jung, SO & Vaddi, R 2015, Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. in ISOCC 2014 - International SoC Design Conference., 7087570, ISOCC 2014 - International SoC Design Conference, Institute of Electrical and Electronics Engineers Inc., pp. 32-33, 11th International SoC Design Conference, ISOCC 2014, Jeju, Korea, Republic of, 14/11/3. https://doi.org/10.1109/ISOCC.2014.7087570

Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. / Kaushal, Gaurav; Subramanyam, K.; Rao, Siva Nageswar; Vidya, G.; Ramya, Radhika; Shaik, Sadulla; Jeong, H.; Jung, S. O.; Vaddi, Ramesh.

ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc., 2015. p. 32-33 7087570 (ISOCC 2014 - International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Kaushal G, Subramanyam K, Rao SN, Vidya G, Ramya R, Shaik S et al. Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. In ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc. 2015. p. 32-33. 7087570. (ISOCC 2014 - International SoC Design Conference). https://doi.org/10.1109/ISOCC.2014.7087570