Abstract
In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically depending on the transfer mode so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event driven simulation and its results show 58% decrease in the data traffic and 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about 56% improvement in the execution time.
| Original language | English |
|---|---|
| Pages | 33-40 |
| Number of pages | 8 |
| Publication status | Published - 1998 Dec 1 |
| Event | Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS - Tainan, China Duration: 1998 Dec 14 → 1998 Dec 16 |
Other
| Other | Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS |
|---|---|
| City | Tainan, China |
| Period | 98/12/14 → 98/12/16 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
Cite this
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Design and performance evaluation of an adaptive cache coherence protocol. / Hong, Won Kee; Kim, Nam Hee; Kim, Shin Dug.
1998. 33-40 Paper presented at Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS, Tainan, China, .Research output: Contribution to conference › Paper
TY - CONF
T1 - Design and performance evaluation of an adaptive cache coherence protocol
AU - Hong, Won Kee
AU - Kim, Nam Hee
AU - Kim, Shin Dug
PY - 1998/12/1
Y1 - 1998/12/1
N2 - In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically depending on the transfer mode so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event driven simulation and its results show 58% decrease in the data traffic and 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about 56% improvement in the execution time.
AB - In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically depending on the transfer mode so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event driven simulation and its results show 58% decrease in the data traffic and 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about 56% improvement in the execution time.
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M3 - Paper
SP - 33
EP - 40
ER -