Design and performance evaluation of an adaptive cache coherence protocol

Won Kee Hong, Nam Hee Kim, Shin Dug Kim

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically depending on the transfer mode so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event driven simulation and its results show 58% decrease in the data traffic and 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about 56% improvement in the execution time.

Original languageEnglish
Pages33-40
Number of pages8
Publication statusPublished - 1998 Dec 1
EventProceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS - Tainan, China
Duration: 1998 Dec 141998 Dec 16

Other

OtherProceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS
CityTainan, China
Period98/12/1498/12/16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Hong, W. K., Kim, N. H., & Kim, S. D. (1998). Design and performance evaluation of an adaptive cache coherence protocol. 33-40. Paper presented at Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS, Tainan, China, .