Abstract
In this paper, we presents efficient hardware design of the slim model of HEVC intra prediction. Our intra prediction module do not use several techniques (TSM, RQT, prediction for 32 × 32 block) used in HM. And several techniques (RMD, RDO) are simplified for hardware design. Though the compression performance is decreased due to this simplification, it allows the hardware implementation of real-time encoder. Real-time Encoder is suitable for IoT because our encoder's size is small and fast. Also the verification of the proposed intra prediction design is conducted. The proposed design was verified via FPGA.
| Original language | English |
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| Title of host publication | ISOCC 2015 - International SoC Design Conference |
| Subtitle of host publication | SoC for Internet of Everything (IoE) |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 283-284 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781467393089 |
| DOIs | |
| Publication status | Published - 2016 Feb 8 |
| Event | 12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of Duration: 2015 Nov 2 → 2015 Nov 5 |
Publication series
| Name | ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) |
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Other
| Other | 12th International SoC Design Conference, ISOCC 2015 |
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| Country/Territory | Korea, Republic of |
| City | Gyeongju |
| Period | 15/11/2 → 15/11/5 |
Bibliographical note
Funding Information:This work was supported by the industrial Core Technology Development Program(10049009, Development of Main IPs for loT and Image Based Security Low-Power SoC) funded by the Ministry of Trade, Industry and Energy. This work was also supported by IDEC(IPC, EDA Tool, MPW)
Publisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials