Design for a turbo-code decoder using a block-wise algorithm

Goo Hyun Park, Suk Hyon Yoon, Daesik Hong, Chang Eon Kang

Research output: Contribution to journalLetter


Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.

Original languageEnglish
Pages (from-to)559-564
Number of pages6
JournalIEICE Transactions on Communications
Issue number2
Publication statusPublished - 2002 Feb


All Science Journal Classification (ASJC) codes

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Park, G. H., Yoon, S. H., Hong, D., & Kang, C. E. (2002). Design for a turbo-code decoder using a block-wise algorithm. IEICE Transactions on Communications, E85-B(2), 559-564.