Design of a 10Gbps analog adaptive equalizer and a pre-emphasis filter for 34-inch backplane channel

Kwisung Yoo; Dongmyung Lee; Gunhee Han; Sungmin Park

Design of a 10Gbps analog adaptive equalizer and a pre-emphasis filter for 34-inch backplane channel

Kwisung Yoo, Dongmyung Lee, Gunhee Han, Sungmin Park

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

Abstract

The serial interface through a backplane channel suffers from severe signal integrity problem caused by channel imperfections such as flat loss, frequency dependent loss, reflection, and so on. The frequency dependent loss is the major cause of ISI (Inter-Symbol Interference). For reducing ISI, a pre-emphasis filter or an adaptive equalizer has been used in many products to overcome the ISI. This paper presents the comparison between these two approaches. Prototype pre-emphasis filter and analog adaptive equalizer are designed with a 0. 18-μm CMOS process for 10G-bps data transmission through a 34-inch FR-4 PCB trace. The simulation and layout results demonstrate 10ps peak-to-peak jitter and 2.24mm² for the pre-emphasis filter and 8ps, peak-to-peak jitter and 0.56mm² for the adaptive equalizer.

Original language	English
Pages (from-to)	1719-1725
Number of pages	7
Journal	WSEAS Transactions on Circuits and Systems
Volume	5
Issue number	12
Publication status	Published - 2006 Dec

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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title = "Design of a 10Gbps analog adaptive equalizer and a pre-emphasis filter for 34-inch backplane channel",

abstract = "The serial interface through a backplane channel suffers from severe signal integrity problem caused by channel imperfections such as flat loss, frequency dependent loss, reflection, and so on. The frequency dependent loss is the major cause of ISI (Inter-Symbol Interference). For reducing ISI, a pre-emphasis filter or an adaptive equalizer has been used in many products to overcome the ISI. This paper presents the comparison between these two approaches. Prototype pre-emphasis filter and analog adaptive equalizer are designed with a 0. 18-μm CMOS process for 10G-bps data transmission through a 34-inch FR-4 PCB trace. The simulation and layout results demonstrate 10ps peak-to-peak jitter and 2.24mm2 for the pre-emphasis filter and 8ps, peak-to-peak jitter and 0.56mm2 for the adaptive equalizer.",

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T1 - Design of a 10Gbps analog adaptive equalizer and a pre-emphasis filter for 34-inch backplane channel

AU - Yoo, Kwisung

AU - Lee, Dongmyung

AU - Han, Gunhee

AU - Park, Sungmin

PY - 2006/12

Y1 - 2006/12

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