Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation

Juhyun Park; Younghwi Yang; Hanwool Jeong; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong Ook Jung

doi:10.1109/TED.2015.2420681

Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation

Juhyun Park, Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

A near-threshold voltage ( V_th) operation circuit is important for both energy-and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-V_th operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-V_th region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-V_th region. This paper proposes a read buffer with adjusted the number of fins or V_th to resolve the problems in the near-V_th region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-V_th region.

Original language	English
Article number	7093154
Pages (from-to)	1698-1704
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	62
Issue number	6
DOIs	https://doi.org/10.1109/TED.2015.2420681
Publication status	Published - 2015 Jun 1

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/TED.2015.2420681

Fingerprint Dive into the research topics of 'Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation'. Together they form a unique fingerprint.

Cite this

@article{d224a338a1df49d5962bf686134866c5,

title = "Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation",

abstract = "A near-threshold voltage ( Vth) operation circuit is important for both energy-and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-Vth operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-Vth region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-Vth region. This paper proposes a read buffer with adjusted the number of fins or Vth to resolve the problems in the near-Vth region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-Vth region.",

author = "Juhyun Park and Younghwi Yang and Hanwool Jeong and Song, {Seung Chul} and Joseph Wang and Geoffrey Yeap and Jung, {Seong Ook}",

year = "2015",

month = jun,

day = "1",

doi = "10.1109/TED.2015.2420681",

language = "English",

volume = "62",

pages = "1698--1704",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation

AU - Park, Juhyun

AU - Yang, Younghwi

AU - Jeong, Hanwool

AU - Song, Seung Chul

AU - Wang, Joseph

AU - Yeap, Geoffrey

AU - Jung, Seong Ook

PY - 2015/6/1

Y1 - 2015/6/1

N2 - A near-threshold voltage ( Vth) operation circuit is important for both energy-and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-Vth operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-Vth region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-Vth region. This paper proposes a read buffer with adjusted the number of fins or Vth to resolve the problems in the near-Vth region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-Vth region.

AB - A near-threshold voltage ( Vth) operation circuit is important for both energy-and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-Vth operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-Vth region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-Vth region. This paper proposes a read buffer with adjusted the number of fins or Vth to resolve the problems in the near-Vth region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-Vth region.

UR - http://www.scopus.com/inward/record.url?scp=85027937076&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027937076&partnerID=8YFLogxK

U2 - 10.1109/TED.2015.2420681

DO - 10.1109/TED.2015.2420681

M3 - Article

AN - SCOPUS:85027937076

VL - 62

SP - 1698

EP - 1704

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 6

M1 - 7093154

ER -