A near-threshold voltage ( Vth) operation circuit is important for both energy-and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-Vth operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-Vth region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-Vth region. This paper proposes a read buffer with adjusted the number of fins or Vth to resolve the problems in the near-Vth region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-Vth region.
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering