Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation

Juhyun Park; Younghwi Yang; Hanwool Jeong; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong Ook Jung

doi:10.1109/TED.2015.2420681

Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation

Juhyun Park, Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

A near-threshold voltage ( V_th) operation circuit is important for both energy-and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-V_th operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-V_th region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-V_th region. This paper proposes a read buffer with adjusted the number of fins or V_th to resolve the problems in the near-V_th region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-V_th region.

Original language	English
Article number	7093154
Pages (from-to)	1698-1704
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	62
Issue number	6
DOIs	https://doi.org/10.1109/TED.2015.2420681
Publication status	Published - 2015 Jun 1

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Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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abstract = "A near-threshold voltage ( Vth) operation circuit is important for both energy-and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-Vth operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-Vth region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-Vth region. This paper proposes a read buffer with adjusted the number of fins or Vth to resolve the problems in the near-Vth region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-Vth region.",

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AU - Wang, Joseph

AU - Yeap, Geoffrey

AU - Jung, Seong Ook

PY - 2015/6/1

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Design of a 22-nm FinFET-based SRAM with read buffer for near-threshold voltage operation

Abstract

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