Design of a bitmap-based QoS-aware memory controller for a packet memory

Seunghak Yu, Sungroh Yoon, Eui Young Chung, Hyuk Jun Lee

Research output: Contribution to journalArticlepeer-review

Abstract

A packet memory controller in routers accesses the packet memory according to the QoS requirements of packets. The previous QoS-aware controller using a feedback control loop degenerates into round robin scheduling under temporary overload and suffers from slow response. We propose a new packet memory controller that estimates input load accurately and rapidly and schedules different classes using a flexible bitmap scheduler. The results show that under temporary overload or rapidly changing input loads, it can successfully meet the latency requirements by showing only less than 2% difference from the requirement of the high priority class.

Original languageEnglish
Article number20130983
Journalieice electronics express
Volume11
Issue number5
DOIs
Publication statusPublished - 2014 Feb 17

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Design of a bitmap-based QoS-aware memory controller for a packet memory'. Together they form a unique fingerprint.

Cite this