Design of high-speed CAVLC decoder architecture for H.264/AVC

Myungseok Oh, Wonjae Lee, Yunho Jung, Jaeseok Kim

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.

Original languageEnglish
Pages (from-to)167-169
Number of pages3
JournalETRI Journal
Volume30
Issue number1
DOIs
Publication statusPublished - 2008 Feb

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Design of high-speed CAVLC decoder architecture for H.264/AVC'. Together they form a unique fingerprint.

  • Cite this