Design of high-speed CAVLC decoder architecture for H.264/AVC

Myungseok Oh, Wonjae Lee, Yunho Jung, Jaeseok Kim

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.

Original languageEnglish
Pages (from-to)167-169
Number of pages3
JournalETRI Journal
Volume30
Issue number1
DOIs
Publication statusPublished - 2008 Feb

Fingerprint

Decoding
Table lookup
Processing
Clocks
Hardware

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Oh, Myungseok ; Lee, Wonjae ; Jung, Yunho ; Kim, Jaeseok. / Design of high-speed CAVLC decoder architecture for H.264/AVC. In: ETRI Journal. 2008 ; Vol. 30, No. 1. pp. 167-169.
@article{03605c7551824bf89798edb3f4503711,
title = "Design of high-speed CAVLC decoder architecture for H.264/AVC",
abstract = "In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.",
author = "Myungseok Oh and Wonjae Lee and Yunho Jung and Jaeseok Kim",
year = "2008",
month = "2",
doi = "10.4218/etrij.08.0207.0208",
language = "English",
volume = "30",
pages = "167--169",
journal = "ETRI Journal",
issn = "1225-6463",
publisher = "ETRI",
number = "1",

}

Design of high-speed CAVLC decoder architecture for H.264/AVC. / Oh, Myungseok; Lee, Wonjae; Jung, Yunho; Kim, Jaeseok.

In: ETRI Journal, Vol. 30, No. 1, 02.2008, p. 167-169.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Design of high-speed CAVLC decoder architecture for H.264/AVC

AU - Oh, Myungseok

AU - Lee, Wonjae

AU - Jung, Yunho

AU - Kim, Jaeseok

PY - 2008/2

Y1 - 2008/2

N2 - In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.

AB - In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.

UR - http://www.scopus.com/inward/record.url?scp=39449119184&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39449119184&partnerID=8YFLogxK

U2 - 10.4218/etrij.08.0207.0208

DO - 10.4218/etrij.08.0207.0208

M3 - Article

AN - SCOPUS:39449119184

VL - 30

SP - 167

EP - 169

JO - ETRI Journal

JF - ETRI Journal

SN - 1225-6463

IS - 1

ER -