This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.
|Number of pages||2|
|Journal||Digest of Technical Papers - IEEE International Conference on Consumer Electronics|
|Publication status||Published - 2000 Jan 1|
All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering