Abstract
This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.
| Original language | English |
|---|---|
| Pages (from-to) | 184-185 |
| Number of pages | 2 |
| Journal | Digest of Technical Papers - IEEE International Conference on Consumer Electronics |
| DOIs | |
| Publication status | Published - 2000 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering
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}
Design of real-time image enhancement preprocessor for CMOS image sensor. / Jung, Yun Ho; Kim, Jae Seok; Hur, Bong Soo; Kang, Moon Gi.
In: Digest of Technical Papers - IEEE International Conference on Consumer Electronics, 01.01.2000, p. 184-185.Research output: Contribution to journal › Article
TY - JOUR
T1 - Design of real-time image enhancement preprocessor for CMOS image sensor
AU - Jung, Yun Ho
AU - Kim, Jae Seok
AU - Hur, Bong Soo
AU - Kang, Moon Gi
PY - 2000/1/1
Y1 - 2000/1/1
N2 - This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.
AB - This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.
UR - http://www.scopus.com/inward/record.url?scp=0033697522&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033697522&partnerID=8YFLogxK
U2 - 10.1109/ICCE.2000.854574
DO - 10.1109/ICCE.2000.854574
M3 - Article
AN - SCOPUS:0033697522
SP - 184
EP - 185
JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
SN - 0747-668X
ER -