Design of real-time image enhancement preprocessor for CMOS image sensor

Yun Ho Jung; Jae Seok Kim; Bong Soo Hur; Moon Gi Kang

doi:10.1109/ICCE.2000.854574

Design of real-time image enhancement preprocessor for CMOS image sensor

Yun Ho Jung, Jae Seok Kim, Bong Soo Hur, Moon Gi Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.

Original language	English
Pages (from-to)	184-185
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
DOIs	https://doi.org/10.1109/ICCE.2000.854574
Publication status	Published - 2000

All Science Journal Classification (ASJC) codes

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ICCE.2000.854574

Cite this

@article{720cd663ba574dbf866d96152a8efcb0,

title = "Design of real-time image enhancement preprocessor for CMOS image sensor",

abstract = "This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.",

author = "Jung, {Yun Ho} and Kim, {Jae Seok} and Hur, {Bong Soo} and Kang, {Moon Gi}",

year = "2000",

doi = "10.1109/ICCE.2000.854574",

language = "English",

pages = "184--185",

journal = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

issn = "0747-668X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Design of real-time image enhancement preprocessor for CMOS image sensor

AU - Jung, Yun Ho

AU - Kim, Jae Seok

AU - Hur, Bong Soo

AU - Kang, Moon Gi

PY - 2000

Y1 - 2000

N2 - This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.

AB - This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on FPGA chip in real-time mode, and performed successfully.

UR - http://www.scopus.com/inward/record.url?scp=0033697522&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033697522&partnerID=8YFLogxK

U2 - 10.1109/ICCE.2000.854574

DO - 10.1109/ICCE.2000.854574

M3 - Article

AN - SCOPUS:0033697522

SP - 184

EP - 185

JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

SN - 0747-668X

ER -

Design of real-time image enhancement preprocessor for CMOS image sensor

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this