Design of the floating-point adder supporting the format conversion and the rounding operations with simultaneous rounding scheme

Woo Chan Park, Cheol Ho Jeong, Tack Don Han

Research output: Contribution to journalArticle

Abstract

The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most cases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.

Original languageEnglish
Pages (from-to)1341-1345
Number of pages5
JournalIEICE Transactions on Information and Systems
VolumeE85-D
Issue number8
Publication statusPublished - 2002 Aug

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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