Design optimization of hybrid-integrated 20-Gb/s optical receivers

Hyun Yong Jung, Jin Sung Youn, Woo-Young Choi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 dB: and 12 GHz, respectively. 20-Gb/s 231-1 electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than 10-12. The receiver circuit has chip area of 0.5 mm × 0.44 mm and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

Original languageEnglish
Pages (from-to)443-450
Number of pages8
JournalJournal of Semiconductor Technology and Science
Volume14
Issue number4
DOIs
Publication statusPublished - 2014 Jan 1

Fingerprint

Optical receivers
Networks (circuits)
Buffers
Operational amplifiers
Photodetectors
Inductance
Capacitance
Wire
Feedback
Differential amplifiers
Design optimization
Polychlorinated Biphenyls
Polychlorinated biphenyls
Equivalent circuits
Bit error rate
Bandwidth
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

@article{fcd1992833a74485a0de723b7f062375,
title = "Design optimization of hybrid-integrated 20-Gb/s optical receivers",
abstract = "This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 dB: and 12 GHz, respectively. 20-Gb/s 231-1 electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than 10-12. The receiver circuit has chip area of 0.5 mm × 0.44 mm and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.",
author = "Jung, {Hyun Yong} and Youn, {Jin Sung} and Woo-Young Choi",
year = "2014",
month = "1",
day = "1",
doi = "10.5573/JSTS.2014.14.4.443",
language = "English",
volume = "14",
pages = "443--450",
journal = "Journal of Semiconductor Technology and Science",
issn = "1598-1657",
publisher = "Institute of Electronics Engineers of Korea",
number = "4",

}

Design optimization of hybrid-integrated 20-Gb/s optical receivers. / Jung, Hyun Yong; Youn, Jin Sung; Choi, Woo-Young.

In: Journal of Semiconductor Technology and Science, Vol. 14, No. 4, 01.01.2014, p. 443-450.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Design optimization of hybrid-integrated 20-Gb/s optical receivers

AU - Jung, Hyun Yong

AU - Youn, Jin Sung

AU - Choi, Woo-Young

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 dB: and 12 GHz, respectively. 20-Gb/s 231-1 electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than 10-12. The receiver circuit has chip area of 0.5 mm × 0.44 mm and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

AB - This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 dB: and 12 GHz, respectively. 20-Gb/s 231-1 electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than 10-12. The receiver circuit has chip area of 0.5 mm × 0.44 mm and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=84906849890&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84906849890&partnerID=8YFLogxK

U2 - 10.5573/JSTS.2014.14.4.443

DO - 10.5573/JSTS.2014.14.4.443

M3 - Article

VL - 14

SP - 443

EP - 450

JO - Journal of Semiconductor Technology and Science

JF - Journal of Semiconductor Technology and Science

SN - 1598-1657

IS - 4

ER -