Design Optimization of Photovoltaic Cell Stacking in a Triple-Well CMOS Process

Geunhee Hong, Gunhee Han

Research output: Contribution to journalArticlepeer-review

Abstract

Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is limited in a standard bulk CMOS process because all the PV cells are intrinsically connected to the common substrate. It is possible to increase the output voltage by stacking multiple PV cells with a large area ratio between stages. However, nonoptimal design results in a poor conversion efficiency or a limited open-circuit voltage, making it unsuitable for practical applications. This article proposes a stacking structure and its optimal design method for PV cell stacking in a triple-well CMOS process. The proposed approach utilizes an additional current-sourcing photodiode and an optical filter, which allow high voltage generation without a significant efficiency degradation. The test chip with four-stage stacked PV cells was fabricated using a 0.25- \mu \text{m} standard triple-well CMOS process. The experimental results demonstrate an output voltage of 1.6 V and an electrical power of 263 nW/mm2 under an incident illumination with an intensity of 96~\mu \text{W} /mm2, achieving a responsivity of 1.91 mA/W and a conversion efficiency of 0.27%.

Original languageEnglish
Article number9078042
Pages (from-to)2381-2385
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume67
Issue number6
DOIs
Publication statusPublished - 2020 Jun

Bibliographical note

Funding Information:
Manuscript received January 31, 2020; revised March 30, 2020; accepted April 2, 2020. Date of publication April 24, 2020; date of current version May 21, 2020. This work was supported by in part the Ministry of Science and ICT (MSIT), South Korea, through the ICT Consilience Creative Program under Grant IITP-2019-2017-0-01015 and in part by the Institute for Information and Communications Technology Promotion (IITP). The review of this article was arranged by Editor B. Hoex. (Corresponding author: Gunhee Han.) The authors are with the School of Integrated Technology, Yonsei University, Incheon 21983, South Korea (e-mail: ghhong@yonsei.ac.kr; gunhee@yonsei.ac.kr).

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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