Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector

This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing a stochastic frequency-phase detector (SFPD). By taking a histogram-based design methodology, optimal weights for both frequency and phase detection are obtained by utilizing the same information as the Alexander phase detector. The design methodology is inductive and stochastic, distinguished from the conventional, deductive, and procedural methods. To verify a robust operation, the effects of varied data patterns, noise, and channel loss are examined, together with the avoidance of harmonic locking. In addition, a consideration of a sample window is analyzed by fast Fourier transform (FFT) simulation. Fabricated in 40-nm low-power (LP) CMOS technology, the proposed CDR circuit achieves a capture range from 6.4 to 32 Gb/s and a lock time of less than <inline-formula> <tex-math notation="LaTeX">11 mu text{s} </tex-math></inline-formula>. The measured frequency acquisition behavior shows that harmonic locking is avoided with a seamless transition to the fundamental mode. The CDR circuit tested over a 10-dB loss channel achieves a bit error rate (BER) less than 10¹² and energy efficiency of 0.96 pJ/b.